From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3EF9C433FE for ; Mon, 20 Sep 2021 12:35:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 81A6D60F4B for ; Mon, 20 Sep 2021 12:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238470AbhITMgy (ORCPT ); Mon, 20 Sep 2021 08:36:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:57594 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233716AbhITMgw (ORCPT ); Mon, 20 Sep 2021 08:36:52 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2134A610A8; Mon, 20 Sep 2021 12:35:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632141326; bh=X6TmFKEMJ7r1hkXSfoYExkSnFh55gCMOKrgmsy914DI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=pLzZa5QmYpjLIjol6Ayc/MzKR4Hw27CIpiTujBs1vhNY2hPr3ddIyLLdAeqs3OHQ4 +M0H0MTN3skkGIAVvub1xrPkn9jUAKTJ8NOfFeuqYAWq0frdTzRyVZ1fxsqCZCBT8H jmNbAtqOAKL3c8etMA5dvtkNsyILHsMdlCE55iIShzxtxlph9u0LRztL0/f2tfpfnR 045Zt9nIBEMIuJfOMW1krCSpZSmGZz8D70JSSv+9ZmGqfkBDXs5ojPGt2yrg2ZCAWo p9H5d43YH4vLtXzr8KShm2jJOna8/eaGashadwhrHvZECZR1UYMMhnM/YseieDodcQ PlSmNkex8H5ag== Received: by mail-ed1-f46.google.com with SMTP id v22so56390753edd.11; Mon, 20 Sep 2021 05:35:26 -0700 (PDT) X-Gm-Message-State: AOAM530ZX4c+WkrD/2/Zoc7qIGiU/p7KqqeB05cE2QJgX1kzxtvJrzF9 +NRXiRZRvr2euCWFMEhUqG957RDMtoO55g2YIg== X-Google-Smtp-Source: ABdhPJwF88jQtPjfNvvL1nKjml4PuXc3iZMNOvFq0Gm0Ol5FfAgq3Zb8NcC/qYhD2qqpX1pKJGAY5SQWfgROQcdI244= X-Received: by 2002:a05:6402:b23:: with SMTP id bo3mr29186170edb.145.1632141324479; Mon, 20 Sep 2021 05:35:24 -0700 (PDT) MIME-Version: 1.0 References: <20210826211830.3311140-1-sean.anderson@seco.com> In-Reply-To: From: Rob Herring Date: Mon, 20 Sep 2021 07:35:12 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 1/3] dt-bindings: pwm: Add Xilinx AXI Timer To: Sean Anderson Cc: Linux PWM List , devicetree@vger.kernel.org, Thierry Reding , Alvaro Gamez , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , linux-arm-kernel , Lee Jones , Michal Simek , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 16, 2021 at 12:58 PM Sean Anderson wrote: > > > > On 8/31/21 4:11 PM, Rob Herring wrote: > > On Thu, Aug 26, 2021 at 05:18:28PM -0400, Sean Anderson wrote: > >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > >> "soft" block, so it has some parameters which would not be configurable in > >> most hardware. This binding is usually automatically generated by Xilinx's > >> tools, so the names and values of some properties should be kept as they > >> are, if possible. In addition, this binding is already in the kernel at > >> arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. > >> > >> The existing driver uses the clock-frequency property, or alternatively the > >> /cpus/timebase-frequency property as its frequency input. Because these > >> properties are deprecated, they have not been included with this schema. > >> All new bindings should use the clocks/clock-names properties to specify > >> the parent clock. > >> > >> Because we need to init timer devices so early in boot, we determine if we > >> should use the PWM driver or the clocksource/clockevent driver by the > >> presence/absence, respectively, of #pwm-cells. Because both counters are > >> used by the PWM, there is no need for a separate property specifying which > >> counters are to be used for the PWM. > >> > >> Signed-off-by: Sean Anderson > >> --- > >> > >> Changes in v6: > >> - Fix incorrect schema id > >> - Enumerate possible counter widths > >> > >> Changes in v5: > >> - Update commit message to reflect revisions > >> - Fix indentation lint > >> - Add example for timer binding > >> - Remove xlnx,axi-timer-2.0 compatible string > >> - Move schema into the timer directory > >> > >> Changes in v4: > >> - Remove references to generate polarity so this can get merged > >> - Predicate PWM driver on the presence of #pwm-cells > >> - Make some properties optional for clocksource drivers > >> > >> Changes in v3: > >> - Mark all boolean-as-int properties as deprecated > >> - Add xlnx,pwm and xlnx,gen?-active-low properties. > >> - Make newer replacement properties mutually-exclusive with what they > >> replace > >> - Add an example with non-deprecated properties only. > >> > >> Changes in v2: > >> - Use 32-bit addresses for example binding > >> > >> .../bindings/timer/xlnx,xps-timer.yaml | 90 +++++++++++++++++++ > >> 1 file changed, 90 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> new file mode 100644 > >> index 000000000000..5be353a642aa > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> @@ -0,0 +1,90 @@ > >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > >> + > >> +maintainers: > >> + - Sean Anderson > >> + > >> +properties: > >> + compatible: > >> + contains: > >> + const: xlnx,xps-timer-1.00.a > >> + > >> + clocks: > >> + maxItems: 1 > >> + > >> + clock-names: > >> + const: s_axi_aclk > >> + > >> + interrupts: > >> + maxItems: 1 > >> + > >> + reg: > >> + maxItems: 1 > >> + > >> + xlnx,count-width: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + enum: [8, 16, 32] > >> + default: 32 > >> + description: > >> + The width of the counter(s), in bits. > >> + > >> + xlnx,one-timer-only: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + enum: [ 0, 1 ] > >> + description: > >> + Whether only one timer is present in this block. > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - xlnx,one-timer-only > >> + > >> +allOf: > >> + - if: > >> + required: > >> + - '#pwm-cells' > >> + then: > >> + allOf: > >> + - required: > >> + - clocks > >> + - properties: > >> + xlnx,one-timer-only: > >> + const: 0 > >> + else: > >> + required: > >> + - interrupts > >> + - if: > >> + required: > >> + - clocks > >> + then: > >> + required: > >> + - clock-names > >> + > >> +additionalProperties: true > > > > This needs to be false. What else do you expect to be present? > > I am going to leave this as true for the next revision to avoid the following error: > > arch/microblaze/boot/dts/system.dt.yaml: timer@83c00000: 'xlnx,family', 'xlnx,gen0-assert', 'xlnx,gen1-assert', 'xlnx,trig0-assert', 'xlnx,trig1-assert' do not match any of the regexes: 'pinctrl-[0-9]+' If I wasn't clear: NAK All properties must be documented or removed from .dts files if not needed. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 702AEC433EF for ; Mon, 20 Sep 2021 12:37:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E54360F4B for ; Mon, 20 Sep 2021 12:37:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3E54360F4B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XFaJ1Ik5psi6gWQLPCMzwXw/EzAqEJGCnPRJyJpk2LY=; b=HRMl4SODWXCvi1 0edEiobi2axzVxHy7AG70aCHML8YCJVkRH8vutRnFM2EIhdpp1kZDlp+WKJZmYRA4QI2V6C3IYP1j xKSiwFHvGzeHKbIqUmo5nZWMt0nv56PSEz2l57fAfveksgsO1HcTTZZnmQf6Et2xxbjPEmCuRFaZi eRk88k+BZyu1V7fFcYWYMif9Nfzd3BBWgM0SNhA7sTYTMLPTHRXSBEzgDNLlVpAhy/YOjzyZidQ9f GxB3W47k5GrPC14uOCDovehNcQ2bB1r865qjwsf4NNeX51CJULiw1VssCPTbh8TqrytBSHH1cZdG/ 1mcOp2PAMRlsh8MI7Iug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSIWC-001and-7j; Mon, 20 Sep 2021 12:35:32 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSIW6-001amI-Rk for linux-arm-kernel@lists.infradead.org; Mon, 20 Sep 2021 12:35:28 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0F9B4610A1 for ; Mon, 20 Sep 2021 12:35:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632141326; bh=X6TmFKEMJ7r1hkXSfoYExkSnFh55gCMOKrgmsy914DI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=pLzZa5QmYpjLIjol6Ayc/MzKR4Hw27CIpiTujBs1vhNY2hPr3ddIyLLdAeqs3OHQ4 +M0H0MTN3skkGIAVvub1xrPkn9jUAKTJ8NOfFeuqYAWq0frdTzRyVZ1fxsqCZCBT8H jmNbAtqOAKL3c8etMA5dvtkNsyILHsMdlCE55iIShzxtxlph9u0LRztL0/f2tfpfnR 045Zt9nIBEMIuJfOMW1krCSpZSmGZz8D70JSSv+9ZmGqfkBDXs5ojPGt2yrg2ZCAWo p9H5d43YH4vLtXzr8KShm2jJOna8/eaGashadwhrHvZECZR1UYMMhnM/YseieDodcQ PlSmNkex8H5ag== Received: by mail-ed1-f47.google.com with SMTP id g8so60866926edt.7 for ; Mon, 20 Sep 2021 05:35:25 -0700 (PDT) X-Gm-Message-State: AOAM532bX6Ey1rLU+Z/QApVxxgsOv8/tXkau2p2VM6ipv1T25hHuLHIW vs6FCIJziJilth9trmqZ+th8b3GaWxD8S4chbA== X-Google-Smtp-Source: ABdhPJwF88jQtPjfNvvL1nKjml4PuXc3iZMNOvFq0Gm0Ol5FfAgq3Zb8NcC/qYhD2qqpX1pKJGAY5SQWfgROQcdI244= X-Received: by 2002:a05:6402:b23:: with SMTP id bo3mr29186170edb.145.1632141324479; Mon, 20 Sep 2021 05:35:24 -0700 (PDT) MIME-Version: 1.0 References: <20210826211830.3311140-1-sean.anderson@seco.com> In-Reply-To: From: Rob Herring Date: Mon, 20 Sep 2021 07:35:12 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 1/3] dt-bindings: pwm: Add Xilinx AXI Timer To: Sean Anderson Cc: Linux PWM List , devicetree@vger.kernel.org, Thierry Reding , Alvaro Gamez , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , linux-arm-kernel , Lee Jones , Michal Simek , "linux-kernel@vger.kernel.org" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210920_053527_002123_A17BF87B X-CRM114-Status: GOOD ( 34.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 16, 2021 at 12:58 PM Sean Anderson wrote: > > > > On 8/31/21 4:11 PM, Rob Herring wrote: > > On Thu, Aug 26, 2021 at 05:18:28PM -0400, Sean Anderson wrote: > >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > >> "soft" block, so it has some parameters which would not be configurable in > >> most hardware. This binding is usually automatically generated by Xilinx's > >> tools, so the names and values of some properties should be kept as they > >> are, if possible. In addition, this binding is already in the kernel at > >> arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. > >> > >> The existing driver uses the clock-frequency property, or alternatively the > >> /cpus/timebase-frequency property as its frequency input. Because these > >> properties are deprecated, they have not been included with this schema. > >> All new bindings should use the clocks/clock-names properties to specify > >> the parent clock. > >> > >> Because we need to init timer devices so early in boot, we determine if we > >> should use the PWM driver or the clocksource/clockevent driver by the > >> presence/absence, respectively, of #pwm-cells. Because both counters are > >> used by the PWM, there is no need for a separate property specifying which > >> counters are to be used for the PWM. > >> > >> Signed-off-by: Sean Anderson > >> --- > >> > >> Changes in v6: > >> - Fix incorrect schema id > >> - Enumerate possible counter widths > >> > >> Changes in v5: > >> - Update commit message to reflect revisions > >> - Fix indentation lint > >> - Add example for timer binding > >> - Remove xlnx,axi-timer-2.0 compatible string > >> - Move schema into the timer directory > >> > >> Changes in v4: > >> - Remove references to generate polarity so this can get merged > >> - Predicate PWM driver on the presence of #pwm-cells > >> - Make some properties optional for clocksource drivers > >> > >> Changes in v3: > >> - Mark all boolean-as-int properties as deprecated > >> - Add xlnx,pwm and xlnx,gen?-active-low properties. > >> - Make newer replacement properties mutually-exclusive with what they > >> replace > >> - Add an example with non-deprecated properties only. > >> > >> Changes in v2: > >> - Use 32-bit addresses for example binding > >> > >> .../bindings/timer/xlnx,xps-timer.yaml | 90 +++++++++++++++++++ > >> 1 file changed, 90 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> new file mode 100644 > >> index 000000000000..5be353a642aa > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > >> @@ -0,0 +1,90 @@ > >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > >> + > >> +maintainers: > >> + - Sean Anderson > >> + > >> +properties: > >> + compatible: > >> + contains: > >> + const: xlnx,xps-timer-1.00.a > >> + > >> + clocks: > >> + maxItems: 1 > >> + > >> + clock-names: > >> + const: s_axi_aclk > >> + > >> + interrupts: > >> + maxItems: 1 > >> + > >> + reg: > >> + maxItems: 1 > >> + > >> + xlnx,count-width: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + enum: [8, 16, 32] > >> + default: 32 > >> + description: > >> + The width of the counter(s), in bits. > >> + > >> + xlnx,one-timer-only: > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + enum: [ 0, 1 ] > >> + description: > >> + Whether only one timer is present in this block. > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - xlnx,one-timer-only > >> + > >> +allOf: > >> + - if: > >> + required: > >> + - '#pwm-cells' > >> + then: > >> + allOf: > >> + - required: > >> + - clocks > >> + - properties: > >> + xlnx,one-timer-only: > >> + const: 0 > >> + else: > >> + required: > >> + - interrupts > >> + - if: > >> + required: > >> + - clocks > >> + then: > >> + required: > >> + - clock-names > >> + > >> +additionalProperties: true > > > > This needs to be false. What else do you expect to be present? > > I am going to leave this as true for the next revision to avoid the following error: > > arch/microblaze/boot/dts/system.dt.yaml: timer@83c00000: 'xlnx,family', 'xlnx,gen0-assert', 'xlnx,gen1-assert', 'xlnx,trig0-assert', 'xlnx,trig1-assert' do not match any of the regexes: 'pinctrl-[0-9]+' If I wasn't clear: NAK All properties must be documented or removed from .dts files if not needed. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel