From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4F6CC48BE0 for ; Fri, 11 Jun 2021 16:07:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 865D7611CD for ; Fri, 11 Jun 2021 16:07:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 865D7611CD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=K3Z0LbbQDrLOT5siq/uxSV1+nScLcvvMKa2p2uIS4s8=; b=Svne2bsUmz9AJH cXpnZgjOBpqBcbp18jfwgCJO7uaS+YQ96vCGQofge4M/sc0UUnNho0Oe+RyTa2qAm5DsIrAPPcD6+ cQ5ZegbZ9kZ6/HaBfeMWUPRtxa4nVROtdqAPdtve/nYw9TgLU0E2tuolZ94i3E1TMmj1HQCF9mCXq lFDb+YuQmj+xVr5Ydggpgr92A2avgBDori5GNJJh4ll9qx/mNLHVInZCTTai57fz3iN6CwwlummhB EmmCV+DmLtsqsNeIeYmta7466WW0u1J2h5l0/YuShfwFE6OGX4nadhQAWCwv9fxBQeddV/YR34Xhj 6eyXIdywsNwd7Nyhpw1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrjem-005uw2-4v; Fri, 11 Jun 2021 16:05:16 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lrjei-005uvM-68 for linux-arm-kernel@lists.infradead.org; Fri, 11 Jun 2021 16:05:13 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6E36E613EA for ; Fri, 11 Jun 2021 16:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1623427511; bh=qQ4a5ohPWGonPGgYyJH/mIM/sJlAHoj8v6OkVH33MDA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Kfin1Odi4ASN+LrXmW97kCB68mc7d+CC6k2itFGOZQZwofNYKKUP18ZR5dI6X3kYs Bp9s+Z9xsQRkQIOjEC3c7tbB5SFZPeg32SBUGqrSk/e18XwslOIG1/JrfexQZWyDlx xrqXcfitxEUECxBlcAvoWZBNcG6gbl61RHg8WPZrR0AgH/pU2uHgsYjyUuXBQPF3Lw RMsS/1KGo4oxDg6ZzN9yzdhWrLiMCcVrkZVj6rnNI06eTTXCLs/V9rqgCbgA60mzJq odeSkjNrJNSjCUXVo8mjehAmeYPL2ca9qMRZxBMGCVHJfhXJn3Hoe0OYtkVBl2O1Gm lLMVL1Iza6phg== Received: by mail-ej1-f41.google.com with SMTP id c10so5286711eja.11 for ; Fri, 11 Jun 2021 09:05:11 -0700 (PDT) X-Gm-Message-State: AOAM532AGMP1VEl47KrSDVqKpmeY2xLykGx9g4Gt8mu/+TQClRcSyWIl Gzg+FHHGfdTT2ciQ8P/8KLG6mTAPCWpk6dvpsw== X-Google-Smtp-Source: ABdhPJwoxLIg8nBWgvR0haj+nsWwjSCXWjRDtcjsZylmpdmu/uXV5GtAGCDJFWVrqu5cMmsequr59KHQrw07ifjhvmE= X-Received: by 2002:a17:906:1d0a:: with SMTP id n10mr4339750ejh.341.1623427510005; Fri, 11 Jun 2021 09:05:10 -0700 (PDT) MIME-Version: 1.0 References: <20210517180256.2881891-1-robh@kernel.org> <20210608152042.GG17957@arm.com> <20210608163459.GA10994@willie-the-truck> In-Reply-To: <20210608163459.GA10994@willie-the-truck> From: Rob Herring Date: Fri, 11 Jun 2021 10:04:57 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2] arm64: Restrict undef hook for cpufeature registers To: Will Deacon Cc: Catalin Marinas , linux-arm-kernel , Raphael Gault X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210611_090512_283224_916C7477 X-CRM114-Status: GOOD ( 29.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jun 8, 2021 at 10:35 AM Will Deacon wrote: > > On Tue, Jun 08, 2021 at 04:20:43PM +0100, Catalin Marinas wrote: > > On Mon, May 17, 2021 at 01:02:56PM -0500, Rob Herring wrote: > > > From: Raphael Gault > > > > > > This commit modifies the mask of the mrs_hook declared in > > > arch/arm64/kernel/cpufeatures.c which emulates only feature register > > > access. This is necessary because this hook's mask was too large and > > > thus masking any mrs instruction, even if not related to the emulated > > > registers which made the pmu emulation inefficient. > > > > > > Signed-off-by: Raphael Gault > > > Signed-off-by: Rob Herring > > > --- > > > I don't *think* I'm going to need this for the perf userspace counter > > > access, but this patch stands on its own as the PMU registers are not > > > emulated. So please apply it. > > > > > > v2: > > > - Fix warning for set but unused sys_reg > > > --- > > > arch/arm64/kernel/cpufeature.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > index efed2830d141..c773f7c3c007 100644 > > > --- a/arch/arm64/kernel/cpufeature.c > > > +++ b/arch/arm64/kernel/cpufeature.c > > > @@ -2905,8 +2905,8 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) > > > } > > > > > > static struct undef_hook mrs_hook = { > > > - .instr_mask = 0xfff00000, > > > - .instr_val = 0xd5300000, > > > + .instr_mask = 0xffff0000, > > > + .instr_val = 0xd5380000, > > > > Acked-by: Catalin Marinas > > > > and changing Will's email address. > > Should we update is_emulated() at the same time, or at least try to generate > the instr_val value here using the same constants? Something like the below patch? We can actually mask a bit more of the instruction (Crn and Crm:3) and then eliminate some of the is_emulated() checks. I'm not all that convinced it's an improvement in readability compared to a raw instr_val and mask nor having is_emulated depend on what was checked in the undef code. diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c773f7c3c007..6b3f50c11ab5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2825,11 +2825,7 @@ static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *c */ static inline bool __attribute_const__ is_emulated(u32 id) { - return (sys_reg_Op0(id) == 0x3 && - sys_reg_CRn(id) == 0x0 && - sys_reg_Op1(id) == 0x0 && - (sys_reg_CRm(id) == 0 || - ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); + return ((sys_reg_CRm(id) == 0) || (sys_reg_CRm(id) >= 4)); } /* @@ -2905,8 +2901,8 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) } static struct undef_hook mrs_hook = { - .instr_mask = 0xffff0000, - .instr_val = 0xd5380000, + .instr_mask = 0xffe00000 | sys_reg(Op0_mask, Op1_mask, CRn_mask, 8, 0), + .instr_val = 0xd5200000 | sys_reg(3, 0, 0, 0, 0), .pstate_mask = PSR_AA32_MODE_MASK, .pstate_val = PSR_MODE_EL0t, .fn = emulate_mrs, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel