From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933975AbcJSCqE convert rfc822-to-8bit (ORCPT ); Tue, 18 Oct 2016 22:46:04 -0400 Received: from mail.kernel.org ([198.145.29.136]:36246 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753233AbcJSCpz (ORCPT ); Tue, 18 Oct 2016 22:45:55 -0400 MIME-Version: 1.0 In-Reply-To: <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> References: <20161017120705.3726-1-wenpan@hisilicon.com> <20161017120705.3726-3-wenpan@hisilicon.com> <20161018155835.qyoffwznacdac46y@rob-hp-laptop> <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> From: Rob Herring Date: Tue, 18 Oct 2016 21:45:29 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC To: Jiancheng Xue Cc: Pan Wen , Michael Turquette , Stephen Boyd , Mark Rutland , Russell King , Wei Xu , linux-clk , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , howell.yang@hisilicon.com, jalen.hsu@hisilicon.com, lvkuanliang 00222834 , suwenping@hisilicon.com, raojun@hisilicon.com, kevin.lixu@hisilicon.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 18, 2016 at 9:38 PM, Jiancheng Xue wrote: > > > 在 2016/10/18 23:58, Rob Herring 写道: >> On Mon, Oct 17, 2016 at 08:07:04PM +0800, Pan Wen wrote: >>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>> Signed-off-by: Pan Wen >>> --- >>> .../devicetree/bindings/clock/hisi-crg.txt | 50 ++++ >>> drivers/clk/hisilicon/Kconfig | 8 + >>> drivers/clk/hisilicon/Makefile | 1 + >>> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++++++++++ >>> drivers/clk/hisilicon/crg.h | 34 +++ >>> include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++ >>> 6 files changed, 471 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt >>> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c >>> create mode 100644 drivers/clk/hisilicon/crg.h >>> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> new file mode 100644 >>> index 0000000..cc60b3d >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> @@ -0,0 +1,50 @@ >>> +* HiSilicon Clock and Reset Generator(CRG) >> >> Seems kind of generic given there's already various HiSi clock bindings >> documented. >> >>> + >>> +The CRG module provides clock and reset signals to various >>> +modules within the SoC. >>> + >>> +This binding uses the following bindings: >>> + Documentation/devicetree/bindings/clock/clock-bindings.txt >>> + Documentation/devicetree/bindings/reset/reset.txt >>> + >>> +Required Properties: >>> + >>> +- compatible: should be one of the following. >>> + - "hisilicon,hi3516cv300-crg" >>> + - "hisilicon,hi3516cv300-sysctrl" >>> + - "hisilicon,hi3519-crg" >> >> There is already a binding for this. Please merge them. >> > Hi Rob, > > Pan Wen and I work together. There's really a same file included in the patch > https://lkml.org/lkml/2016/9/18/42 ([PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC). > But that patch has not been acked. This binding file will be merged if that > patch is accepted first. Could you give me more comments on that patch or > help me to ack it? Thank you very much. If I haven't commented, then likely it was not sent to the DT list. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC Date: Tue, 18 Oct 2016 21:45:29 -0500 Message-ID: References: <20161017120705.3726-1-wenpan@hisilicon.com> <20161017120705.3726-3-wenpan@hisilicon.com> <20161018155835.qyoffwznacdac46y@rob-hp-laptop> <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> Sender: linux-clk-owner@vger.kernel.org To: Jiancheng Xue Cc: Pan Wen , Michael Turquette , Stephen Boyd , Mark Rutland , Russell King , Wei Xu , linux-clk , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , howell.yang@hisilicon.com, jalen.hsu@hisilicon.com, lvkuanliang 00222834 , suwenping@hisilicon.com, raojun@hisilicon.com, kevin.lixu@hisilicon.com List-Id: devicetree@vger.kernel.org On Tue, Oct 18, 2016 at 9:38 PM, Jiancheng Xue wrote: > > > 在 2016/10/18 23:58, Rob Herring 写道: >> On Mon, Oct 17, 2016 at 08:07:04PM +0800, Pan Wen wrote: >>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>> Signed-off-by: Pan Wen >>> --- >>> .../devicetree/bindings/clock/hisi-crg.txt | 50 ++++ >>> drivers/clk/hisilicon/Kconfig | 8 + >>> drivers/clk/hisilicon/Makefile | 1 + >>> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++++++++++ >>> drivers/clk/hisilicon/crg.h | 34 +++ >>> include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++ >>> 6 files changed, 471 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt >>> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c >>> create mode 100644 drivers/clk/hisilicon/crg.h >>> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> new file mode 100644 >>> index 0000000..cc60b3d >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> @@ -0,0 +1,50 @@ >>> +* HiSilicon Clock and Reset Generator(CRG) >> >> Seems kind of generic given there's already various HiSi clock bindings >> documented. >> >>> + >>> +The CRG module provides clock and reset signals to various >>> +modules within the SoC. >>> + >>> +This binding uses the following bindings: >>> + Documentation/devicetree/bindings/clock/clock-bindings.txt >>> + Documentation/devicetree/bindings/reset/reset.txt >>> + >>> +Required Properties: >>> + >>> +- compatible: should be one of the following. >>> + - "hisilicon,hi3516cv300-crg" >>> + - "hisilicon,hi3516cv300-sysctrl" >>> + - "hisilicon,hi3519-crg" >> >> There is already a binding for this. Please merge them. >> > Hi Rob, > > Pan Wen and I work together. There's really a same file included in the patch > https://lkml.org/lkml/2016/9/18/42 ([PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC). > But that patch has not been acked. This binding file will be merged if that > patch is accepted first. Could you give me more comments on that patch or > help me to ack it? Thank you very much. If I haven't commented, then likely it was not sent to the DT list. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> References: <20161017120705.3726-1-wenpan@hisilicon.com> <20161017120705.3726-3-wenpan@hisilicon.com> <20161018155835.qyoffwznacdac46y@rob-hp-laptop> <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> From: Rob Herring Date: Tue, 18 Oct 2016 21:45:29 -0500 Message-ID: Subject: Re: [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC To: Jiancheng Xue Cc: Pan Wen , Michael Turquette , Stephen Boyd , Mark Rutland , Russell King , Wei Xu , linux-clk , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , howell.yang@hisilicon.com, jalen.hsu@hisilicon.com, lvkuanliang 00222834 , suwenping@hisilicon.com, raojun@hisilicon.com, kevin.lixu@hisilicon.com Content-Type: text/plain; charset=UTF-8 List-ID: On Tue, Oct 18, 2016 at 9:38 PM, Jiancheng Xue wrote: > > > =E5=9C=A8 2016/10/18 23:58, Rob Herring =E5=86=99=E9=81=93: >> On Mon, Oct 17, 2016 at 08:07:04PM +0800, Pan Wen wrote: >>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>> Signed-off-by: Pan Wen >>> --- >>> .../devicetree/bindings/clock/hisi-crg.txt | 50 ++++ >>> drivers/clk/hisilicon/Kconfig | 8 + >>> drivers/clk/hisilicon/Makefile | 1 + >>> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++= ++++++++ >>> drivers/clk/hisilicon/crg.h | 34 +++ >>> include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++ >>> 6 files changed, 471 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.tx= t >>> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c >>> create mode 100644 drivers/clk/hisilicon/crg.h >>> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Doc= umentation/devicetree/bindings/clock/hisi-crg.txt >>> new file mode 100644 >>> index 0000000..cc60b3d >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> @@ -0,0 +1,50 @@ >>> +* HiSilicon Clock and Reset Generator(CRG) >> >> Seems kind of generic given there's already various HiSi clock bindings >> documented. >> >>> + >>> +The CRG module provides clock and reset signals to various >>> +modules within the SoC. >>> + >>> +This binding uses the following bindings: >>> + Documentation/devicetree/bindings/clock/clock-bindings.txt >>> + Documentation/devicetree/bindings/reset/reset.txt >>> + >>> +Required Properties: >>> + >>> +- compatible: should be one of the following. >>> + - "hisilicon,hi3516cv300-crg" >>> + - "hisilicon,hi3516cv300-sysctrl" >>> + - "hisilicon,hi3519-crg" >> >> There is already a binding for this. Please merge them. >> > Hi Rob, > > Pan Wen and I work together. There's really a same file included in the p= atch > https://lkml.org/lkml/2016/9/18/42 ([PATCH v2] clk: hisilicon: add CRG dr= iver for Hi3798CV200 SoC). > But that patch has not been acked. This binding file will be merged if th= at > patch is accepted first. Could you give me more comments on that patch or > help me to ack it? Thank you very much. If I haven't commented, then likely it was not sent to the DT list. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Tue, 18 Oct 2016 21:45:29 -0500 Subject: [PATCH 2/3] clk: hisilicon: add CRG driver for Hi3516CV300 SoC In-Reply-To: <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> References: <20161017120705.3726-1-wenpan@hisilicon.com> <20161017120705.3726-3-wenpan@hisilicon.com> <20161018155835.qyoffwznacdac46y@rob-hp-laptop> <7ce2e35b-19e1-9493-90a7-15b321fee2cc@hisilicon.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Oct 18, 2016 at 9:38 PM, Jiancheng Xue wrote: > > > ? 2016/10/18 23:58, Rob Herring ??: >> On Mon, Oct 17, 2016 at 08:07:04PM +0800, Pan Wen wrote: >>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>> Signed-off-by: Pan Wen >>> --- >>> .../devicetree/bindings/clock/hisi-crg.txt | 50 ++++ >>> drivers/clk/hisilicon/Kconfig | 8 + >>> drivers/clk/hisilicon/Makefile | 1 + >>> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 +++++++++++++++++++++ >>> drivers/clk/hisilicon/crg.h | 34 +++ >>> include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++ >>> 6 files changed, 471 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/hisi-crg.txt >>> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c >>> create mode 100644 drivers/clk/hisilicon/crg.h >>> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> new file mode 100644 >>> index 0000000..cc60b3d >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt >>> @@ -0,0 +1,50 @@ >>> +* HiSilicon Clock and Reset Generator(CRG) >> >> Seems kind of generic given there's already various HiSi clock bindings >> documented. >> >>> + >>> +The CRG module provides clock and reset signals to various >>> +modules within the SoC. >>> + >>> +This binding uses the following bindings: >>> + Documentation/devicetree/bindings/clock/clock-bindings.txt >>> + Documentation/devicetree/bindings/reset/reset.txt >>> + >>> +Required Properties: >>> + >>> +- compatible: should be one of the following. >>> + - "hisilicon,hi3516cv300-crg" >>> + - "hisilicon,hi3516cv300-sysctrl" >>> + - "hisilicon,hi3519-crg" >> >> There is already a binding for this. Please merge them. >> > Hi Rob, > > Pan Wen and I work together. There's really a same file included in the patch > https://lkml.org/lkml/2016/9/18/42 ([PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC). > But that patch has not been acked. This binding file will be merged if that > patch is accepted first. Could you give me more comments on that patch or > help me to ack it? Thank you very much. If I haven't commented, then likely it was not sent to the DT list. Rob