From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752886AbdA3R3d (ORCPT ); Mon, 30 Jan 2017 12:29:33 -0500 Received: from mail.kernel.org ([198.145.29.136]:46034 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751419AbdA3R3b (ORCPT ); Mon, 30 Jan 2017 12:29:31 -0500 MIME-Version: 1.0 In-Reply-To: References: <20170122122219.10611-1-linus.walleij@linaro.org> <20170123202105.qslqna4ckeyfwame@rob-hp-laptop> From: Rob Herring Date: Mon, 30 Jan 2017 11:21:27 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini To: Linus Walleij Cc: "linux-arm-kernel@lists.infradead.org" , Hans Ulli Kroll , Florian Fainelli , Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, Arnd Bergmann , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jan 28, 2017 at 3:56 PM, Linus Walleij wrote: > On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring wrote: >> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote: >>> This adds the top level SoC bindings for Cortina systems Gemini >>> platforms. > (...) >>> +- intcon: the root node must have an interrupt controller node pointing to >> >> intcon is just a source label and not meaningful for the binding. > > OK > >>> +Example: >>> + >>> +/ { >>> + interrupt-parent = <&intcon>; >>> + >>> + syscon: syscon@40000000 { >> >> This chip has no internal bus? Put all these nodes under a bus. > > Are you thinking something of the form: > > soc: soc { > #address-cells = <1>; > #size-cells = <1>; > ranges; > compatible = "simple-bus"; > > syscon: syscon@40000000 { > > (...) > > ? Yes. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini Date: Mon, 30 Jan 2017 11:21:27 -0600 Message-ID: References: <20170122122219.10611-1-linus.walleij@linaro.org> <20170123202105.qslqna4ckeyfwame@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Linus Walleij Cc: openwrt-devel@openwrt.org, "devicetree@vger.kernel.org" , Florian Fainelli , Arnd Bergmann , Paulius Zaleckas , Hans Ulli Kroll , "linux-kernel@vger.kernel.org" , Janos Laube , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org On Sat, Jan 28, 2017 at 3:56 PM, Linus Walleij wrote: > On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring wrote: >> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote: >>> This adds the top level SoC bindings for Cortina systems Gemini >>> platforms. > (...) >>> +- intcon: the root node must have an interrupt controller node pointing to >> >> intcon is just a source label and not meaningful for the binding. > > OK > >>> +Example: >>> + >>> +/ { >>> + interrupt-parent = <&intcon>; >>> + >>> + syscon: syscon@40000000 { >> >> This chip has no internal bus? Put all these nodes under a bus. > > Are you thinking something of the form: > > soc: soc { > #address-cells = <1>; > #size-cells = <1>; > ranges; > compatible = "simple-bus"; > > syscon: syscon@40000000 { > > (...) > > ? Yes. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Mon, 30 Jan 2017 11:21:27 -0600 Subject: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini In-Reply-To: References: <20170122122219.10611-1-linus.walleij@linaro.org> <20170123202105.qslqna4ckeyfwame@rob-hp-laptop> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sat, Jan 28, 2017 at 3:56 PM, Linus Walleij wrote: > On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring wrote: >> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote: >>> This adds the top level SoC bindings for Cortina systems Gemini >>> platforms. > (...) >>> +- intcon: the root node must have an interrupt controller node pointing to >> >> intcon is just a source label and not meaningful for the binding. > > OK > >>> +Example: >>> + >>> +/ { >>> + interrupt-parent = <&intcon>; >>> + >>> + syscon: syscon at 40000000 { >> >> This chip has no internal bus? Put all these nodes under a bus. > > Are you thinking something of the form: > > soc: soc { > #address-cells = <1>; > #size-cells = <1>; > ranges; > compatible = "simple-bus"; > > syscon: syscon at 40000000 { > > (...) > > ? Yes. Rob