From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYKqT-0007Wq-Ti for qemu-devel@nongnu.org; Thu, 10 Apr 2014 15:41:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WYKqS-00055t-K5 for qemu-devel@nongnu.org; Thu, 10 Apr 2014 15:41:09 -0400 Received: from mail-vc0-x229.google.com ([2607:f8b0:400c:c03::229]:62257) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYKqS-00055k-Fm for qemu-devel@nongnu.org; Thu, 10 Apr 2014 15:41:08 -0400 Received: by mail-vc0-f169.google.com with SMTP id ik5so4033064vcb.28 for ; Thu, 10 Apr 2014 12:41:07 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> <1394134385-1727-22-git-send-email-peter.maydell@linaro.org> Date: Thu, 10 Apr 2014 14:41:07 -0500 Message-ID: From: Rob Herring Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] [PATCH v4 21/21] hw/arm/virt: Add support for Cortex-A57 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Peter Crosthwaite , Patch Tracking , Michael Matz , "qemu-devel@nongnu.org Developers" , Will Newton , Dirk Mueller , Laurent Desnogues , "kvmarm@lists.cs.columbia.edu" , Richard Henderson On Thu, Apr 10, 2014 at 10:02 AM, Peter Maydell wrote: > On 17 March 2014 07:12, Peter Crosthwaite wrote: >> On Fri, Mar 7, 2014 at 5:33 AM, Peter Maydell wrote: >>> Support the Cortex-A57 in the virt machine model. >>> >>> Signed-off-by: Peter Maydell >>> --- >>> This should perhaps not be just stealing the a15mpcore_priv >>> on the basis that it's a GICv2... >> >> Wont this mean you gets lots of extraneous hardware? Although, with a >> pure virtual machine I guess you can do whatever you really want. > > No, a15mpcore_priv only has a GIC in it. > >>> --- >>> hw/arm/virt.c | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c >>> index 517f2fe..d985d2e 100644 >>> --- a/hw/arm/virt.c >>> +++ b/hw/arm/virt.c >>> @@ -123,6 +123,14 @@ static VirtBoardInfo machines[] = { >>> .irqmap = a15irqmap, >>> }, >>> { >>> + .cpu_model = "cortex-a57", >>> + /* Use the A15 private peripheral model for now: probably wrong! */ >>> + .qdevname = "a15mpcore_priv", >> >> Can you just change this to gics qdev name? The qdev propnames of gic >> and mpcore ("num-cpu" and "num-irq") should just match. Then perhaps a >> little callback to set gicv2 version property. > > That would miss the other thing a15mpcore_priv does for us, > which is to wire up the generic timer outputs from the CPU > objects to the appropriate GIC inputs. (Also the gpio_in > lines on a15mpcore_priv and the gic itself are not the > same: a15mpcore_priv only exposise the SPIs.) > > We could in theory write an a57mpcore_priv which was a > carbon copy of a15mpcore_priv, but that seems a bit pointless. > I think it's probably actually reasonable to use a15mpcore_priv > here, with an appropriate comment: > > /* Our A57 has an A15-style GICv2, so we can use a15mpcore_priv */ I think there are 3 possibilities of what actual h/w may look like. i agree this is the correct thing to do for one case (and is the only one qemu is able to support today). The others are: A57 + SBSA compliant GICv2(M) A57 + GICv3 The SBSA change is making each register bank within the GIC 64K spaced instead of 4K spaced to support 64KB pages in OSs and hypervisors. This is a simple address swizzling trick defined in the SBSA doc. (Since it's documented it must not be a cute embedded nonsense hack. :)) Then the M portion is for PCI MSI support which is optional. Rob