From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v4 22/22] phy: Add support for Qualcomm's USB HS phy Date: Mon, 19 Sep 2016 16:01:09 -0500 Message-ID: References: <20160907213519.27340-1-stephen.boyd@linaro.org> <20160907213519.27340-23-stephen.boyd@linaro.org> <20160916151950.GA31804@rob-hp-laptop> <147407072439.8245.12292695359399379462@sboyd-linaro> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Received: from mail.kernel.org ([198.145.29.136]:60092 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932163AbcISVBf (ORCPT ); Mon, 19 Sep 2016 17:01:35 -0400 In-Reply-To: <147407072439.8245.12292695359399379462@sboyd-linaro> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Stephen Boyd Cc: Linux USB List , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , linux-arm-msm , Andy Gross , Bjorn Andersson , Neil Armstrong , Arnd Bergmann , Felipe Balbi , Peter Chen , Kishon Vijay Abraham I , "devicetree@vger.kernel.org" On Fri, Sep 16, 2016 at 7:05 PM, Stephen Boyd wrote: > Quoting Rob Herring (2016-09-16 08:19:51) >> On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote: >> > The high-speed phy on qcom SoCs is controlled via the ULPI >> > viewport. >> > [...] >> > +- qcom,init-seq: >> > + Usage: optional >> > + Value type: >> > + Definition: Should contain a sequence of ULPI register and address pairs to >> > + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related >> > + to Device Mode Eye Diagram test. >> >> We generally nak this type of property. For 1 register I don't care so >> much. For 100, that would be another story. >> >> Is this value per unit, per board, per SoC? Can you limit it to certain >> registers? > > I'm told that this can be per board, depending on how it's wired from > the phy pins to the usb port. Typically it's the same though for the > boards I have, mostly because those boards are similar designs with > respect to how USB is wired. The set of registers is not that many, 4 or > 5 at most. My understanding is these are tuning registers. Right now the > register part in the binding is the full register offset, and not an > offset from ULPI_EXT_VENDOR_SPECIFIC (0x80). I could change this to be > an offset from that area if you like so that this can't be abused to > write into standard ULPI registers (there really isn't any way to > enforce this in software though). Okay, that sounds fine to me. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932462AbcISVBh (ORCPT ); Mon, 19 Sep 2016 17:01:37 -0400 Received: from mail.kernel.org ([198.145.29.136]:60092 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932163AbcISVBf (ORCPT ); Mon, 19 Sep 2016 17:01:35 -0400 MIME-Version: 1.0 In-Reply-To: <147407072439.8245.12292695359399379462@sboyd-linaro> References: <20160907213519.27340-1-stephen.boyd@linaro.org> <20160907213519.27340-23-stephen.boyd@linaro.org> <20160916151950.GA31804@rob-hp-laptop> <147407072439.8245.12292695359399379462@sboyd-linaro> From: Rob Herring Date: Mon, 19 Sep 2016 16:01:09 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 22/22] phy: Add support for Qualcomm's USB HS phy To: Stephen Boyd Cc: Linux USB List , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , linux-arm-msm , Andy Gross , Bjorn Andersson , Neil Armstrong , Arnd Bergmann , Felipe Balbi , Peter Chen , Kishon Vijay Abraham I , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 16, 2016 at 7:05 PM, Stephen Boyd wrote: > Quoting Rob Herring (2016-09-16 08:19:51) >> On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote: >> > The high-speed phy on qcom SoCs is controlled via the ULPI >> > viewport. >> > [...] >> > +- qcom,init-seq: >> > + Usage: optional >> > + Value type: >> > + Definition: Should contain a sequence of ULPI register and address pairs to >> > + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related >> > + to Device Mode Eye Diagram test. >> >> We generally nak this type of property. For 1 register I don't care so >> much. For 100, that would be another story. >> >> Is this value per unit, per board, per SoC? Can you limit it to certain >> registers? > > I'm told that this can be per board, depending on how it's wired from > the phy pins to the usb port. Typically it's the same though for the > boards I have, mostly because those boards are similar designs with > respect to how USB is wired. The set of registers is not that many, 4 or > 5 at most. My understanding is these are tuning registers. Right now the > register part in the binding is the full register offset, and not an > offset from ULPI_EXT_VENDOR_SPECIFIC (0x80). I could change this to be > an offset from that area if you like so that this can't be abused to > write into standard ULPI registers (there really isn't any way to > enforce this in software though). Okay, that sounds fine to me. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Mon, 19 Sep 2016 16:01:09 -0500 Subject: [PATCH v4 22/22] phy: Add support for Qualcomm's USB HS phy In-Reply-To: <147407072439.8245.12292695359399379462@sboyd-linaro> References: <20160907213519.27340-1-stephen.boyd@linaro.org> <20160907213519.27340-23-stephen.boyd@linaro.org> <20160916151950.GA31804@rob-hp-laptop> <147407072439.8245.12292695359399379462@sboyd-linaro> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Sep 16, 2016 at 7:05 PM, Stephen Boyd wrote: > Quoting Rob Herring (2016-09-16 08:19:51) >> On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote: >> > The high-speed phy on qcom SoCs is controlled via the ULPI >> > viewport. >> > [...] >> > +- qcom,init-seq: >> > + Usage: optional >> > + Value type: >> > + Definition: Should contain a sequence of ULPI register and address pairs to >> > + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related >> > + to Device Mode Eye Diagram test. >> >> We generally nak this type of property. For 1 register I don't care so >> much. For 100, that would be another story. >> >> Is this value per unit, per board, per SoC? Can you limit it to certain >> registers? > > I'm told that this can be per board, depending on how it's wired from > the phy pins to the usb port. Typically it's the same though for the > boards I have, mostly because those boards are similar designs with > respect to how USB is wired. The set of registers is not that many, 4 or > 5 at most. My understanding is these are tuning registers. Right now the > register part in the binding is the full register offset, and not an > offset from ULPI_EXT_VENDOR_SPECIFIC (0x80). I could change this to be > an offset from that area if you like so that this can't be abused to > write into standard ULPI registers (there really isn't any way to > enforce this in software though). Okay, that sounds fine to me. Rob