From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79E62C433EF for ; Wed, 20 Oct 2021 18:48:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52F696103D for ; Wed, 20 Oct 2021 18:48:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231331AbhJTSuW (ORCPT ); Wed, 20 Oct 2021 14:50:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:35640 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230076AbhJTSuR (ORCPT ); Wed, 20 Oct 2021 14:50:17 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0A10E6103D; Wed, 20 Oct 2021 18:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634755683; bh=n8VrOe4I2yKWKENo2xOz+GrW26l+tosuZNQ1rYD5gKE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=X8tKojH7Z8fdPyVTk4z+AoVAS3a9h5oYDEVDa7uI3b3vQWDC0RDkopnsSuFW09wMx S5ymoCHlxw+BZDcfi8a/SbXyaru92R/D/4JVacWcGVpk2lCHkMZKGKNpRCcpV4amQE 0SC95mBmBf+xrbZsPKYOZ3Tw+i6Awvb4CDoD4fADso7xeFCGtNQbQjFeERWiYt5J4a XviC1MWcQkWkyhnJbBbb7MhB9KdUgixAetlN+ZjGulMI+TYlz6yOX8pi/IJu8QIrAm DPTPSRiUO2vc4Q2/LyUL9rJoQfRdVbdcu/SicgghaP/nLNsd5aIhVOahGYlBk3gw4h jokZEwKpwMQ/g== Received: by mail-lf1-f42.google.com with SMTP id g36so328184lfv.3; Wed, 20 Oct 2021 11:48:02 -0700 (PDT) X-Gm-Message-State: AOAM532bXNhmVLh6cfAOUxsJB+NDo+eiCLht4tPeKR4iEnlNWXGLeu4P /I69BmJlS2QuRZe9tLV1khZkLcBv1KlsB4zS7g== X-Google-Smtp-Source: ABdhPJyDkQcU37hcsbyKe6namKZuEksRA+CPb1y/N+dx0XKOp77yba3905ZumF5lcfjyaXaZElnjUUGJ+2NqhJwXc9g= X-Received: by 2002:aa7:cd0a:: with SMTP id b10mr942298edw.164.1634755670808; Wed, 20 Oct 2021 11:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20211006164332.1981454-1-robh@kernel.org> In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> From: Rob Herring Date: Wed, 20 Oct 2021 13:47:39 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support To: Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , X86 ML , Greg Kroah-Hartman Cc: Florian Fainelli , Ray Jui , Scott Branden , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Rafael J. Wysocki" , Frank Rowand , linux-arm-kernel , "linux-kernel@vger.kernel.org" , linux-csky@vger.kernel.org, Openrisc , linuxppc-dev , linux-riscv , SH-Linux , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote: > > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. > > Rob > > Rob Herring (12): > of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes > ARM: Use of_get_cpu_hwid() > ARM: broadcom: Use of_get_cpu_hwid() > arm64: Use of_get_cpu_hwid() > csky: Use of_get_cpu_hwid() > openrisc: Use of_get_cpu_hwid() > powerpc: Use of_get_cpu_hwid() > riscv: Use of_get_cpu_hwid() > sh: Use of_get_cpu_hwid() > x86: dt: Use of_get_cpu_hwid() > cacheinfo: Allow for >32-bit cache 'id' > cacheinfo: Set cache 'id' based on DT data I've fixed up the openrisc error and applied 1-10 to the DT tree. The cacheinfo part is going to need some more work. I've found I will need the cache affinity (of possible cpus) as well, so I plan to also store the affinity instead of looping thru caches and cpus again. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC2A1C433EF for ; Wed, 20 Oct 2021 18:48:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EF026103D for ; Wed, 20 Oct 2021 18:48:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8EF026103D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aSl4sXbuq3xzuXSxZLE/Sa6BLt8rlzNWI/Uj59N+A/Q=; b=QTbBYtvgoteRrs PHX+SKrNuyjSs3BCmmbcnMvaixV9LBxLJwZrvOR3iI4yXk24FaWHMiLw9xfKmuieOWu+62FMZkpDx R1cMHjBEVAsAHL6CZpRYJ1F+DTJ+Vt3OqGHz1CqtM1sKdW6j5CreX1AeWwzfViiQn/SUmZZwWl20U 6LhuJ/gPG2+GAu9fT0Br1A1tJcLskmWIVT51VTavSI7PfV0U97VaTw7wokMm2uHDZnpC2s5riqGYb d36AAH5CcqRvQ1FUDHOwZDPNmunIWHpjdfJ7ALYqW7vJMmS+t9ZDWz4JpDJT8HZwi8B4t4Vvd7mDc cEEE0pdfmqYtH8hIseRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdGdM-005VQP-60; Wed, 20 Oct 2021 18:48:16 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdGd9-005VNp-G6; Wed, 20 Oct 2021 18:48:04 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2C52D61038; Wed, 20 Oct 2021 18:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634755683; bh=n8VrOe4I2yKWKENo2xOz+GrW26l+tosuZNQ1rYD5gKE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=X8tKojH7Z8fdPyVTk4z+AoVAS3a9h5oYDEVDa7uI3b3vQWDC0RDkopnsSuFW09wMx S5ymoCHlxw+BZDcfi8a/SbXyaru92R/D/4JVacWcGVpk2lCHkMZKGKNpRCcpV4amQE 0SC95mBmBf+xrbZsPKYOZ3Tw+i6Awvb4CDoD4fADso7xeFCGtNQbQjFeERWiYt5J4a XviC1MWcQkWkyhnJbBbb7MhB9KdUgixAetlN+ZjGulMI+TYlz6yOX8pi/IJu8QIrAm DPTPSRiUO2vc4Q2/LyUL9rJoQfRdVbdcu/SicgghaP/nLNsd5aIhVOahGYlBk3gw4h jokZEwKpwMQ/g== Received: by mail-ed1-f47.google.com with SMTP id t16so276606eds.9; Wed, 20 Oct 2021 11:48:03 -0700 (PDT) X-Gm-Message-State: AOAM532z4p26pRQHpJgW/DYpUto2rwOOACz7Imc/dbWIRzxSXWLpys4D B2g915QLXeuBdN8UJmCJf+Bev2B0uMsvSjpy5Q== X-Google-Smtp-Source: ABdhPJyDkQcU37hcsbyKe6namKZuEksRA+CPb1y/N+dx0XKOp77yba3905ZumF5lcfjyaXaZElnjUUGJ+2NqhJwXc9g= X-Received: by 2002:aa7:cd0a:: with SMTP id b10mr942298edw.164.1634755670808; Wed, 20 Oct 2021 11:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20211006164332.1981454-1-robh@kernel.org> In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> From: Rob Herring Date: Wed, 20 Oct 2021 13:47:39 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support To: Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , X86 ML , Greg Kroah-Hartman Cc: Florian Fainelli , Ray Jui , Scott Branden , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Rafael J. Wysocki" , Frank Rowand , linux-arm-kernel , "linux-kernel@vger.kernel.org" , linux-csky@vger.kernel.org, Openrisc , linuxppc-dev , linux-riscv , SH-Linux , devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_114803_586536_1C72BD80 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote: > > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. > > Rob > > Rob Herring (12): > of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes > ARM: Use of_get_cpu_hwid() > ARM: broadcom: Use of_get_cpu_hwid() > arm64: Use of_get_cpu_hwid() > csky: Use of_get_cpu_hwid() > openrisc: Use of_get_cpu_hwid() > powerpc: Use of_get_cpu_hwid() > riscv: Use of_get_cpu_hwid() > sh: Use of_get_cpu_hwid() > x86: dt: Use of_get_cpu_hwid() > cacheinfo: Allow for >32-bit cache 'id' > cacheinfo: Set cache 'id' based on DT data I've fixed up the openrisc error and applied 1-10 to the DT tree. The cacheinfo part is going to need some more work. I've found I will need the cache affinity (of possible cpus) as well, so I plan to also store the affinity instead of looping thru caches and cpus again. Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC18AC433F5 for ; Wed, 20 Oct 2021 18:48:47 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29D9161038 for ; Wed, 20 Oct 2021 18:48:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 29D9161038 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HZKQ52zDMz3bc4 for ; Thu, 21 Oct 2021 05:48:45 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=X8tKojH7; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=198.145.29.99; helo=mail.kernel.org; envelope-from=robh@kernel.org; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=X8tKojH7; dkim-atps=neutral Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HZKPL4Q4rz2xv0 for ; Thu, 21 Oct 2021 05:48:06 +1100 (AEDT) Received: by mail.kernel.org (Postfix) with ESMTPSA id 58C8A610D0 for ; Wed, 20 Oct 2021 18:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634755683; bh=n8VrOe4I2yKWKENo2xOz+GrW26l+tosuZNQ1rYD5gKE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=X8tKojH7Z8fdPyVTk4z+AoVAS3a9h5oYDEVDa7uI3b3vQWDC0RDkopnsSuFW09wMx S5ymoCHlxw+BZDcfi8a/SbXyaru92R/D/4JVacWcGVpk2lCHkMZKGKNpRCcpV4amQE 0SC95mBmBf+xrbZsPKYOZ3Tw+i6Awvb4CDoD4fADso7xeFCGtNQbQjFeERWiYt5J4a XviC1MWcQkWkyhnJbBbb7MhB9KdUgixAetlN+ZjGulMI+TYlz6yOX8pi/IJu8QIrAm DPTPSRiUO2vc4Q2/LyUL9rJoQfRdVbdcu/SicgghaP/nLNsd5aIhVOahGYlBk3gw4h jokZEwKpwMQ/g== Received: by mail-wr1-f41.google.com with SMTP id r10so273179wra.12 for ; Wed, 20 Oct 2021 11:48:03 -0700 (PDT) X-Gm-Message-State: AOAM532Izt7zxxvzCH2EiOrM8D4J9xFqEu2GoIyAwpPXRU9RA4qIlX6q X2LGDJQA6R1endHT/2x81EhuqemR5el0NrCW/g== X-Google-Smtp-Source: ABdhPJyDkQcU37hcsbyKe6namKZuEksRA+CPb1y/N+dx0XKOp77yba3905ZumF5lcfjyaXaZElnjUUGJ+2NqhJwXc9g= X-Received: by 2002:aa7:cd0a:: with SMTP id b10mr942298edw.164.1634755670808; Wed, 20 Oct 2021 11:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20211006164332.1981454-1-robh@kernel.org> In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> From: Rob Herring Date: Wed, 20 Oct 2021 13:47:39 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support To: Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , X86 ML , Greg Kroah-Hartman Content-Type: text/plain; charset="UTF-8" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Florian Fainelli , Scott Branden , "Rafael J. Wysocki" , SH-Linux , Ray Jui , "H. Peter Anvin" , "linux-kernel@vger.kernel.org" , linux-csky@vger.kernel.org, Openrisc , linuxppc-dev , Ingo Molnar , Paul Mackerras , Borislav Petkov , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Thomas Gleixner , Frank Rowand , linux-riscv , linux-arm-kernel Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote: > > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. > > Rob > > Rob Herring (12): > of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes > ARM: Use of_get_cpu_hwid() > ARM: broadcom: Use of_get_cpu_hwid() > arm64: Use of_get_cpu_hwid() > csky: Use of_get_cpu_hwid() > openrisc: Use of_get_cpu_hwid() > powerpc: Use of_get_cpu_hwid() > riscv: Use of_get_cpu_hwid() > sh: Use of_get_cpu_hwid() > x86: dt: Use of_get_cpu_hwid() > cacheinfo: Allow for >32-bit cache 'id' > cacheinfo: Set cache 'id' based on DT data I've fixed up the openrisc error and applied 1-10 to the DT tree. The cacheinfo part is going to need some more work. I've found I will need the cache affinity (of possible cpus) as well, so I plan to also store the affinity instead of looping thru caches and cpus again. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47C0DC433F5 for ; Wed, 20 Oct 2021 18:49:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15E0E61038 for ; Wed, 20 Oct 2021 18:49:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 15E0E61038 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ot7/KBMimGsA5SP7Hb6dDxVBBC2V3gW+4CpoI3HbY2c=; b=z4WlOtoGgPxVcc fzRJPyL1w2psuOO8YtacAx32X3bwsqvLjDWzcKq6z6IUnnjX4FK8NQfC59+PJBUPbdYU/oUq8Km4P 0uXZGpYNB+Q7aq51rp6QPw5SAplY3UgL3BPOAyWYk2DNMgYIM5BM9efzRP+u/Z+5TyNlOFZfTZKyq D8W+zMSx2hcDKHeAdmDgqyTLK/zEgSkXAkR1DFO91c2XU8sAZTRrCX61VNmkTldBpyCGIqyqaKC3f 4q+svu4hXun1LOfhTM95p5NYnVsAMjlEO6eFhtrKKAmv4/Fk6dIyGsdyamaa6BcdNCDufXOjMQfFA p5Pg4pyFMUk62RwlXZmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdGdD-005VOK-3p; Wed, 20 Oct 2021 18:48:07 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdGd9-005VNp-G6; Wed, 20 Oct 2021 18:48:04 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2C52D61038; Wed, 20 Oct 2021 18:48:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634755683; bh=n8VrOe4I2yKWKENo2xOz+GrW26l+tosuZNQ1rYD5gKE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=X8tKojH7Z8fdPyVTk4z+AoVAS3a9h5oYDEVDa7uI3b3vQWDC0RDkopnsSuFW09wMx S5ymoCHlxw+BZDcfi8a/SbXyaru92R/D/4JVacWcGVpk2lCHkMZKGKNpRCcpV4amQE 0SC95mBmBf+xrbZsPKYOZ3Tw+i6Awvb4CDoD4fADso7xeFCGtNQbQjFeERWiYt5J4a XviC1MWcQkWkyhnJbBbb7MhB9KdUgixAetlN+ZjGulMI+TYlz6yOX8pi/IJu8QIrAm DPTPSRiUO2vc4Q2/LyUL9rJoQfRdVbdcu/SicgghaP/nLNsd5aIhVOahGYlBk3gw4h jokZEwKpwMQ/g== Received: by mail-ed1-f47.google.com with SMTP id t16so276606eds.9; Wed, 20 Oct 2021 11:48:03 -0700 (PDT) X-Gm-Message-State: AOAM532z4p26pRQHpJgW/DYpUto2rwOOACz7Imc/dbWIRzxSXWLpys4D B2g915QLXeuBdN8UJmCJf+Bev2B0uMsvSjpy5Q== X-Google-Smtp-Source: ABdhPJyDkQcU37hcsbyKe6namKZuEksRA+CPb1y/N+dx0XKOp77yba3905ZumF5lcfjyaXaZElnjUUGJ+2NqhJwXc9g= X-Received: by 2002:aa7:cd0a:: with SMTP id b10mr942298edw.164.1634755670808; Wed, 20 Oct 2021 11:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20211006164332.1981454-1-robh@kernel.org> In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> From: Rob Herring Date: Wed, 20 Oct 2021 13:47:39 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support To: Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , X86 ML , Greg Kroah-Hartman Cc: Florian Fainelli , Ray Jui , Scott Branden , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Rafael J. Wysocki" , Frank Rowand , linux-arm-kernel , "linux-kernel@vger.kernel.org" , linux-csky@vger.kernel.org, Openrisc , linuxppc-dev , linux-riscv , SH-Linux , devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_114803_586536_1C72BD80 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote: > > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. > > Rob > > Rob Herring (12): > of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes > ARM: Use of_get_cpu_hwid() > ARM: broadcom: Use of_get_cpu_hwid() > arm64: Use of_get_cpu_hwid() > csky: Use of_get_cpu_hwid() > openrisc: Use of_get_cpu_hwid() > powerpc: Use of_get_cpu_hwid() > riscv: Use of_get_cpu_hwid() > sh: Use of_get_cpu_hwid() > x86: dt: Use of_get_cpu_hwid() > cacheinfo: Allow for >32-bit cache 'id' > cacheinfo: Set cache 'id' based on DT data I've fixed up the openrisc error and applied 1-10 to the DT tree. The cacheinfo part is going to need some more work. I've found I will need the cache affinity (of possible cpus) as well, so I plan to also store the affinity instead of looping thru caches and cpus again. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Date: Wed, 20 Oct 2021 13:47:39 -0500 Subject: [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> References: <20211006164332.1981454-1-robh@kernel.org> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org On Wed, Oct 6, 2021 at 11:43 AM Rob Herring wrote: > > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. > > Rob > > Rob Herring (12): > of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes > ARM: Use of_get_cpu_hwid() > ARM: broadcom: Use of_get_cpu_hwid() > arm64: Use of_get_cpu_hwid() > csky: Use of_get_cpu_hwid() > openrisc: Use of_get_cpu_hwid() > powerpc: Use of_get_cpu_hwid() > riscv: Use of_get_cpu_hwid() > sh: Use of_get_cpu_hwid() > x86: dt: Use of_get_cpu_hwid() > cacheinfo: Allow for >32-bit cache 'id' > cacheinfo: Set cache 'id' based on DT data I've fixed up the openrisc error and applied 1-10 to the DT tree. The cacheinfo part is going to need some more work. I've found I will need the cache affinity (of possible cpus) as well, so I plan to also store the affinity instead of looping thru caches and cpus again. Rob