From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE0EEC7618F for ; Mon, 15 Jul 2019 17:03:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C7CD22080A for ; Mon, 15 Jul 2019 17:03:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563210229; bh=rjrlrnQPDBPyEI2VvOI7m0hccqKp54THKXzQCNuj7e8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=kbyMrPbirrZElxsHNnwTVlc/DPgHSZVeqKCee0dWmx84zY4p3Lazun+2BP9BqQgzM xmx6NROB1+k5BLtt3OjhkvBynky6wvD/JodM9VssuAbK7rvO7fpD+++wVdyN7KcB3T ChCC8HSecUZBRucZXcnK8WwpA+CttQHJy0CiKCmU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730914AbfGORDp (ORCPT ); Mon, 15 Jul 2019 13:03:45 -0400 Received: from mail.kernel.org ([198.145.29.99]:51330 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730782AbfGORDp (ORCPT ); Mon, 15 Jul 2019 13:03:45 -0400 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 454392080A; Mon, 15 Jul 2019 17:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563210224; bh=rjrlrnQPDBPyEI2VvOI7m0hccqKp54THKXzQCNuj7e8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=rD0dF+yCPBgLJ83N++laHPgUXgCYGAMz72tCRtdR8UGZKaN70hvg/XOtOAQglbDmg G89e88qOwY2fe8WqBu5ApgXpAqOOVcczcWs2prqWcWewX7h8rF6gJN105q/T1aiRvU USG4hd3jDr+PTIiK0elLNX7e1NozVpX8HYEvRdtA= Received: by mail-qt1-f181.google.com with SMTP id w17so16369330qto.10; Mon, 15 Jul 2019 10:03:44 -0700 (PDT) X-Gm-Message-State: APjAAAX64xkwZdlrM4yLU4NvYSbGWek+DmWwPIoiRU2QI344R+MHMJ8w Ibzodl8cqPpnLXXTnse2h/eJHJ+Sni+uGwKpJQ== X-Google-Smtp-Source: APXvYqwJvWYWvEZ7jhvuIO0kny3nJ2FG1ki4BA/d03vXMpzs2ob165VOtQejHnSTXliJm/t+yYCx8Ni0kj3f+zn0LUM= X-Received: by 2002:ac8:368a:: with SMTP id a10mr19043100qtc.143.1563210223567; Mon, 15 Jul 2019 10:03:43 -0700 (PDT) MIME-Version: 1.0 References: <20190713034634.44585-1-icenowy@aosc.io> <20190713034634.44585-8-icenowy@aosc.io> In-Reply-To: <20190713034634.44585-8-icenowy@aosc.io> From: Rob Herring Date: Mon, 15 Jul 2019 11:03:32 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , Linus Walleij , devicetree@vger.kernel.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , linux-clk , "open list:GPIO SUBSYSTEM" , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Date: Mon, 15 Jul 2019 11:03:32 -0600 Message-ID: References: <20190713034634.44585-1-icenowy@aosc.io> <20190713034634.44585-8-icenowy@aosc.io> Reply-To: robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190713034634.44585-8-icenowy-h8G6r0blFSE@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , Linus Walleij , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , linux-clk , "open list:GPIO SUBSYSTEM" , linux-sunxi List-Id: devicetree@vger.kernel.org On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C813C76195 for ; Mon, 15 Jul 2019 17:03:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5419920838 for ; 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Mon, 15 Jul 2019 17:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563210224; bh=rjrlrnQPDBPyEI2VvOI7m0hccqKp54THKXzQCNuj7e8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=rD0dF+yCPBgLJ83N++laHPgUXgCYGAMz72tCRtdR8UGZKaN70hvg/XOtOAQglbDmg G89e88qOwY2fe8WqBu5ApgXpAqOOVcczcWs2prqWcWewX7h8rF6gJN105q/T1aiRvU USG4hd3jDr+PTIiK0elLNX7e1NozVpX8HYEvRdtA= Received: by mail-qt1-f181.google.com with SMTP id r6so12196889qtt.0 for ; Mon, 15 Jul 2019 10:03:44 -0700 (PDT) X-Gm-Message-State: APjAAAWrv2y9/S5KwGIbsF96LLqB9oq/50Em0IZOteqxsMuckXbznYsA eX7b44poVY+iADQjT0fAEV/11SvcTX+RmK74Wg== X-Google-Smtp-Source: APXvYqwJvWYWvEZ7jhvuIO0kny3nJ2FG1ki4BA/d03vXMpzs2ob165VOtQejHnSTXliJm/t+yYCx8Ni0kj3f+zn0LUM= X-Received: by 2002:ac8:368a:: with SMTP id a10mr19043100qtc.143.1563210223567; Mon, 15 Jul 2019 10:03:43 -0700 (PDT) MIME-Version: 1.0 References: <20190713034634.44585-1-icenowy@aosc.io> <20190713034634.44585-8-icenowy@aosc.io> In-Reply-To: <20190713034634.44585-8-icenowy@aosc.io> From: Rob Herring Date: Mon, 15 Jul 2019 11:03:32 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board To: Icenowy Zheng X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_100345_928815_33581CFE X-CRM114-Status: GOOD ( 13.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Maxime Ripard , Linus Walleij , linux-sunxi , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Chen-Yu Tsai , linux-clk , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel