From mboxrd@z Thu Jan 1 00:00:00 1970 From: Minkyu Kang Date: Tue, 24 Jul 2012 17:58:10 +0900 Subject: [U-Boot] [V2 11/15] S3C64XX: Switch to use read/writel to operation clock system In-Reply-To: <1342195913-25161-12-git-send-email-bocui107@gmail.com> References: <1342195913-25161-1-git-send-email-bocui107@gmail.com> <1342195913-25161-12-git-send-email-bocui107@gmail.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Zhong Hongbo, On 14 July 2012 01:11, Zhong Hongbo wrote: > From: Zhong Hongbo > > Switch to use read/writel function and clear the relevant variable. > > Signed-off-by: Zhong Hongbo > --- > Change for V2: > - merge clock patch. > - Change the type of return for s3c64xx_get_base_clock function. > --- > arch/arm/cpu/arm1176/s3c64xx/reset.S | 4 +- > arch/arm/cpu/arm1176/s3c64xx/speed.c | 50 +++++-- > arch/arm/include/asm/arch-s3c64xx/clock.h | 147 ++++++++++++++++++ > arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 219 +-------------------------- > board/samsung/smdk6400/lowlevel_init.S | 64 ++++----- > drivers/usb/host/s3c64xx-hcd.c | 30 ++++- > 6 files changed, 243 insertions(+), 271 deletions(-) > create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h > > diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S > index eae572e..9e5ee84 100644 > --- a/arch/arm/cpu/arm1176/s3c64xx/reset.S > +++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S > @@ -26,9 +26,9 @@ > .globl reset_cpu > reset_cpu: > ldr r1, =ELFIN_CLOCK_POWER_BASE > - ldr r2, [r1, #SYS_ID_OFFSET] > + ldr r2, [r1, #0x118] @ SYS_ID_OFFSET > ldr r3, =0xffff > and r2, r3, r2, lsr #12 > - str r2, [r1, #SW_RST_OFFSET] > + str r2, [r1, #0x114] @ SW_RST_OFFSET Don't use magic numbers. And I think this file can be converted to C file. > _loop_forever: > b _loop_forever > diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S > index 6cc7567..79d5ab3 100644 > --- a/board/samsung/smdk6400/lowlevel_init.S > +++ b/board/samsung/smdk6400/lowlevel_init.S > @@ -106,7 +106,7 @@ lowlevel_init: > #endif > > /* Wakeup support. Don't know if it's going to be used, untested. */ > - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) > + ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0x904) @ RST_STAT_OFFSET > ldr r1, [r0] > bic r1, r1, #0xfffffff7 > cmp r1, #0x8 > @@ -119,23 +119,24 @@ lowlevel_init: > wakeup_reset: > > /* Clear wakeup status register */ > - ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) > + ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0x908) @ WAKEUP_STAT_OFFSET > ldr r1, [r0] > str r1, [r0] > > /* LED test */ > ldr r0, =ELFIN_GPIO_BASE > ldr r1, =0x3000 > - str r1, [r0, #GPNDAT_OFFSET] > + str r1, [r0, #0x834] @ GPNDAT_OFFSET > > /* Load return address and jump to kernel */ > - ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) > + ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0xa00) @ INF_REG0_OFFSET > /* r1 = physical address of s3c6400_cpu_resume function */ > ldr r1, [r0] > /* Jump to kernel (sleep-s3c6400.S) */ > mov pc, r1 > nop > nop > + > /* > * system_clock_init: Initialize core clock and bus clock. > * void system_clock_init(void) > @@ -144,10 +145,10 @@ system_clock_init: > ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ > > #ifdef CONFIG_SYNC_MODE > - ldr r1, [r0, #OTHERS_OFFSET] > + ldr r1, [r0, #0x900] @ OTHERS_OFFSET > mov r2, #0x40 > orr r1, r1, r2 > - str r1, [r0, #OTHERS_OFFSET] > + str r1, [r0, #0x900] > > nop > nop > @@ -157,10 +158,10 @@ system_clock_init: > > ldr r2, =0x80 > orr r1, r1, r2 > - str r1, [r0, #OTHERS_OFFSET] > + str r1, [r0, #0x900] > > check_syncack: > - ldr r1, [r0, #OTHERS_OFFSET] > + ldr r1, [r0, #0x900] > ldr r2, =0xf00 > and r1, r1, r2 > cmp r1, #0xf00 > @@ -177,69 +178,58 @@ check_syncack: > * seem to make much sense on S3C6400. > */ > #ifndef CONFIG_S3C6400 > - ldr r1, [r0, #OTHERS_OFFSET] > + ldr r1, [r0, #0x900] @ OTHERS_OFFSET > bic r1, r1, #0xC0 > orr r1, r1, #0x40 > - str r1, [r0, #OTHERS_OFFSET] > + str r1, [r0, #0x900] > > wait_for_async: > - ldr r1, [r0, #OTHERS_OFFSET] > + ldr r1, [r0, #0x900] @ OTHERS_OFFSET > and r1, r1, #0xf00 > cmp r1, #0x0 > bne wait_for_async > #endif > > - ldr r1, [r0, #OTHERS_OFFSET] > + ldr r1, [r0, #0x900] @ OTHERS_OFFSET > bic r1, r1, #0x40 > - str r1, [r0, #OTHERS_OFFSET] > + str r1, [r0, #0x900] > #endif > > mov r1, #0xff00 > orr r1, r1, #0xff > - str r1, [r0, #APLL_LOCK_OFFSET] > - str r1, [r0, #MPLL_LOCK_OFFSET] > + str r1, [r0, #0x0] @ APLL_LOCK_OFFSET > + str r1, [r0, #0x4] @ MPLL_LOCK_OFFSET > > /* Set Clock Divider */ > - ldr r1, [r0, #CLK_DIV0_OFFSET] > + ldr r1, [r0, #0x20] @ CLK_DIV0_OFFSET > bic r1, r1, #0x30000 > bic r1, r1, #0xff00 > bic r1, r1, #0xff > - ldr r2, =CLK_DIV_VAL > + ldr r2, =0x3310 > orr r1, r1, r2 > - str r1, [r0, #CLK_DIV0_OFFSET] > + str r1, [r0, #0x20] > > - ldr r1, =APLL_VAL > - str r1, [r0, #APLL_CON_OFFSET] > - ldr r1, =MPLL_VAL > - str r1, [r0, #MPLL_CON_OFFSET] > + ldr r1, =0x82150601 > + str r1, [r0, #0x0c] @ APLL_CON_OFFSET > + ldr r1, =0x82150601 > + str r1, [r0, #0x10] @ MPLL_CON_OFFSET > > /* FOUT of EPLL is 96MHz */ > ldr r1, =0x200203 > - str r1, [r0, #EPLL_CON0_OFFSET] > + str r1, [r0, #0x14] @ EPLL_CON0_OFFSET > ldr r1, =0x0 > - str r1, [r0, #EPLL_CON1_OFFSET] > + str r1, [r0, #0x18] @ EPLL_CON1_OFFSET > > /* APLL, MPLL, EPLL select to Fout */ > - ldr r1, [r0, #CLK_SRC_OFFSET] > + ldr r1, [r0, #0x1c] @ CLK_SRC_OFFSET > orr r1, r1, #0x7 > - str r1, [r0, #CLK_SRC_OFFSET] > + str r1, [r0, #0x1c] > > /* wait at least 200us to stablize all clock */ > mov r1, #0x10000 > 1: subs r1, r1, #1 > bne 1b > > - /* Synchronization for VIC port */ > -#if defined(CONFIG_SYNC_MODE) > - ldr r1, [r0, #OTHERS_OFFSET] > - orr r1, r1, #0x20 > - str r1, [r0, #OTHERS_OFFSET] > -#elif !defined(CONFIG_S3C6400) > - /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */ > - ldr r1, [r0, #OTHERS_OFFSET] > - bic r1, r1, #0x20 > - str r1, [r0, #OTHERS_OFFSET] > -#endif > mov pc, lr > Too many magic numbers. Please fix it globally. Thanks. Minkyu Kang. -- from. prom. www.promsoft.net