From mboxrd@z Thu Jan  1 00:00:00 1970
From: Minkyu Kang <promsoft@gmail.com>
Date: Thu, 14 Nov 2013 10:56:10 +0900
Subject: [U-Boot] [PATCH 03/10 V6] Exynos5420: Add clock initialization
 for 5420
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	<CAPs=JDduJwyadrwt06UFOF7LbOrPme-1gDoeyoShxRmMYt4o_g@mail.gmail.com>
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Dear Rajeshwari,


On 13 November 2013 20:17, Rajeshwari Birje <rajeshwari.birje@gmail.com>wrote:

> Hi Minkyu Kang,
>
> Thank you for comments,
>
> On Wed, Nov 13, 2013 at 8:15 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> > Dear Rajeshwari S Shinde,
> >
> >
> > On 29 October 2013 16:23, Rajeshwari S Shinde <rajeshwari.s@samsung.com
> >wrote:
> >
> >> This patch adds code for clock initialization and clock settings
> >> of various IP's and controllers, required for Exynos5420
> >>
> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
> >> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> ---
> >> Changes in V2:
> >>         - None
> >> Changes in V3:
> >>         - None
> >> Changes in V4:
> >>         - Corrected the multiline commenting style
> >> Changes in V5:
> >>         - None
> >> Changes in V6:
> >>         - None
> >>  arch/arm/cpu/armv7/exynos/clock.c              | 270 ++++++++-
> >>  arch/arm/cpu/armv7/exynos/clock_init.h         |  17 +
> >>  arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++-
> >>  arch/arm/cpu/armv7/exynos/exynos5_setup.h      | 740
> >> +++++++++++++++++++------
> >>  arch/arm/include/asm/arch-exynos/clk.h         |   1 +
> >>  arch/arm/include/asm/arch-exynos/clock.h       | 494 +++++++++++++++++
> >>  6 files changed, 1673 insertions(+), 201 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> >> b/arch/arm/cpu/armv7/exynos/clock.c
> >> index 36fedd6..b52e61a 100644
> >> --- a/arch/arm/cpu/armv7/exynos/clock.c
> >> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> >> @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> >> r, unsigned int k)
> >>
> >>         freq = CONFIG_SYS_CLK_FREQ;
> >>
> >> -       if (pllreg == EPLL) {
> >> +       if (pllreg == EPLL || pllreg == RPLL) {
> >>                 k = k & 0xffff;
> >>                 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
> >>                 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 <<
> s)));
> >> @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned
> int
> >> r, unsigned int k)
> >>                         div = PLL_DIV_1024;
> >>                 else if (proid_is_exynos4412())
> >>                         div = PLL_DIV_65535;
> >> -               else if (proid_is_exynos5250())
> >> +               else if (cpu_is_exynos5())
> >>
> >
> > please don't mix proid_is... and cpu_is...
> Since both 5420 and 5250 need same value added cpu_is_exynos5(),
> instead of doing a or of both.
>

I know, but this if statement for proid..
then, you should use same statement.

you can do this.

else if (proid_is_exynos5250() || prois_is_exynos5420())

or

if (cpu_is_exynos4()) {
    if (proid_is....) {
    } else if (proid_is....) {
    }
} else if (cpu_is_exynos5()) {
    .....
}


Thanks,
Minkyu Kang.
-- 
from. prom.
www.promsoft.net