From: Saeed Mahameed <saeedm@dev.mellanox.co.il>
To: Daniel Jurgens <danielj@mellanox.com>
Cc: David Laight <David.Laight@aculab.com>,
Saeed Mahameed <saeedm@mellanox.com>,
"David S. Miller" <davem@davemloft.net>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: Re: [net-next 2/8] net/mlx5: Configure cache line size for start and end padding
Date: Sun, 5 Feb 2017 13:23:41 +0200 [thread overview]
Message-ID: <CALzJLG_v7kZrioA_VrHT78iatiEOSCp9uWUJFNv1XP6+sMvFzQ@mail.gmail.com> (raw)
In-Reply-To: <VI1PR0501MB2429398983643A6387BE91D0C44C0@VI1PR0501MB2429.eurprd05.prod.outlook.com>
On Thu, Feb 2, 2017 at 4:47 PM, Daniel Jurgens <danielj@mellanox.com> wrote:
> On 2/1/2017 5:12 AM, David Laight wrote:
>> From: Saeed Mahameed
>>> Sent: 31 January 2017 20:59
>>> From: Daniel Jurgens <danielj@mellanox.com>
>>>
>>> There is a hardware feature that will pad the start or end of a DMA to
>>> be cache line aligned to avoid RMWs on the last cache line. The default
>>> cache line size setting for this feature is 64B. This change configures
>>> the hardware to use 128B alignment on systems with 128B cache lines.
>> What guarantees that the extra bytes are actually inside the receive skb's
>> head and tail room?
>>
>> David
>>
>>
> The hardware won't over write the length of the posted buffer. This feature is already enabled and defaults to 64B stride, this patch just configures it properly for 128B cache line sizes.
>
Right, and next patch will make sure RX stride is aligned to 128B in
case 128B cacheline size configured into the HW.
> Thanks for reviewing it.
>
> Dan
>
next prev parent reply other threads:[~2017-02-05 11:24 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-31 20:58 [pull request][net-next 0/8] Mellanox mlx5 updates 2017-01-31 Saeed Mahameed
2017-01-31 20:58 ` [net-next 1/8] net/mlx5: Fixed static checker warnings Saeed Mahameed
2017-02-01 11:17 ` David Laight
2017-02-01 16:39 ` Or Gerlitz
2017-02-01 17:02 ` David Laight
2017-02-01 17:22 ` David Miller
2017-02-01 23:48 ` Or Gerlitz
2017-01-31 20:58 ` [net-next 2/8] net/mlx5: Configure cache line size for start and end padding Saeed Mahameed
2017-02-01 11:12 ` David Laight
2017-02-02 14:47 ` Daniel Jurgens
2017-02-05 11:23 ` Saeed Mahameed [this message]
2017-02-06 13:50 ` David Laight
2017-02-06 14:26 ` Saeed Mahameed
2017-01-31 20:58 ` [net-next 3/8] net/mlx5e: Lower bound MPWRQ stride by HCA cacheline Saeed Mahameed
2017-01-31 20:58 ` [net-next 4/8] net/mlx5: TX WQE update Saeed Mahameed
2017-01-31 20:58 ` [net-next 5/8] net/mlx5e: Calc vlan_tag_present only once on xmit Saeed Mahameed
2017-02-01 11:20 ` David Laight
2017-02-05 11:22 ` Saeed Mahameed
2017-01-31 20:58 ` [net-next 6/8] net/mlx5e: Tx, no inline copy on ConnectX-5 Saeed Mahameed
2017-01-31 20:58 ` [net-next 7/8] net/mlx5e: XDP " Saeed Mahameed
2017-01-31 20:58 ` [net-next 8/8] net/mlx5e: Bring back bfreg uar map dedicated pointer Saeed Mahameed
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