From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E6E1C48BE0 for ; Fri, 11 Jun 2021 14:33:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2D2A6100B for ; Fri, 11 Jun 2021 14:33:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2D2A6100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lriEG-0002vR-4B for qemu-devel@archiver.kernel.org; Fri, 11 Jun 2021 10:33:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lriCz-0000He-Bh for qemu-devel@nongnu.org; Fri, 11 Jun 2021 10:32:29 -0400 Received: from mail-yb1-xb34.google.com ([2607:f8b0:4864:20::b34]:41707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lriCu-0003Jj-Lp for qemu-devel@nongnu.org; Fri, 11 Jun 2021 10:32:29 -0400 Received: by mail-yb1-xb34.google.com with SMTP id q21so4583862ybg.8 for ; Fri, 11 Jun 2021 07:32:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2sTxXr5gC959k1+XB9dQaAhITr9tEAfw1eda2OLASbY=; b=YS94sf5MuM7P7bK0fHVf0fJay/vnnYgPoF0tRtnpC3LXH/kwGV/P3Pqk/E2SCS7Z1N vr3IN5Cgkrbr5P4lFNoDEf6+c0tGEZqBKH3k8tjw8D0sj6GtLaQ5PdnRhj3NG8j/niSH 4CAPWZ/TQPVRuIRq2wZQ/xqa6QjPvhZ7Yi7TIDQEPl3JZFsRFVpZkYBnBIxSsb/3ntUN b5bjpWObIY3IqqxhOR9fU/qo/bAQYAsY/cFdV1bNdJl36nNr6awGUdvT5+n5fE85b4cP ApWAvbsOOfDWhIG5XeH1NV7expyGEBtLRF5zBIroin5UGlbToUVYJWrobJgW97p4wd4o y2aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2sTxXr5gC959k1+XB9dQaAhITr9tEAfw1eda2OLASbY=; b=L+8BNKLGkKp+ZGgYB3jE4XTOQmbJ5WfESzO3V2ouVhh93faxLYN5j23NglUtk1TaPy sxudxBmM6poelhsijqsseYRr64fuBX7fawpW7VWZ9u58uJ6bexoaDc71hjPll+6++I/p 10xx0lTCe+hazaJbdACZjCdS8IeL5sKAtP8aHMeTZoQdie1wB28wmgj9ktG8yR4q4hr2 tbCqJJNjmk+XpqvzMMMy+/q2aP78ArwDZQ8E9b6f+txWtAZGpJ4jiRZblajCioYHMo9i hY9c888zcOWm727d0UnjSg68A/hly10qg6VEPO2GM0SlNNSarfbA094npF/zQWndSyZq ueiA== X-Gm-Message-State: AOAM530eVhSVO10wy50AS/+moiZG3Z4DbPJ56HpgCEgcQfhF1MKzzxJO sA8H1jBRJB7uAYr3+CS2TgGaeWIu+t9vLsHrqZIE6Vwx80s= X-Google-Smtp-Source: ABdhPJwHP7Xc7o0YKpGxKM68trIDcnF7gtGDWxGLXrNfuNdmkUj9i9cNwdBvea1C6PMT0u6jYe5wIAdo66bGVYB9G9E= X-Received: by 2002:a25:8191:: with SMTP id p17mr6255578ybk.405.1623421942697; Fri, 11 Jun 2021 07:32:22 -0700 (PDT) MIME-Version: 1.0 References: <20210530150112.74411-1-ziqiaokong@gmail.com> In-Reply-To: From: Ziqiao Kong Date: Fri, 11 Jun 2021 22:32:11 +0800 Message-ID: Subject: Re: [PATCH v7 1/2] target/i386: Trivial code motion and code style fix To: QEMU Developers Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=ziqiaokong@gmail.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ping. On Fri, Jun 4, 2021 at 11:04 PM Ziqiao Kong wrote: > > Ping. > > Sorry again for the previous duplicate emails. > > On Sun, May 30, 2021 at 11:03 PM Ziqiao Kong wrote: > > > > A new pair of braces has to be added to declare variables in the case block. > > The code style is also fixed according to the transalte.c itself during the > > code motion. > > > > Signed-off-by: Ziqiao Kong > > --- > > Sorry for the duplicate emails due to my bad network. The v7 has no > > difference from v6 and is sent just for clarification. > > Changes since v5: > > - None > > Changes since v4: > > - Rewrite commit message to specify the reason to add the braces. > > --- > > target/i386/tcg/translate.c | 957 ++++++++++++++++++------------------ > > 1 file changed, 484 insertions(+), 473 deletions(-) > > > > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > > index 834186bcae..5c1b7b87c5 100644 > > --- a/target/i386/tcg/translate.c > > +++ b/target/i386/tcg/translate.c > > @@ -5929,503 +5929,514 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > > /************************/ > > /* floats */ > > case 0xd8 ... 0xdf: > > - if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { > > - /* if CR0.EM or CR0.TS are set, generate an FPU exception */ > > - /* XXX: what to do if illegal op ? */ > > - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); > > - break; > > - } > > - modrm = x86_ldub_code(env, s); > > - mod = (modrm >> 6) & 3; > > - rm = modrm & 7; > > - op = ((b & 7) << 3) | ((modrm >> 3) & 7); > > - if (mod != 3) { > > - /* memory op */ > > - gen_lea_modrm(env, s, modrm); > > - switch(op) { > > - case 0x00 ... 0x07: /* fxxxs */ > > - case 0x10 ... 0x17: /* fixxxl */ > > - case 0x20 ... 0x27: /* fxxxl */ > > - case 0x30 ... 0x37: /* fixxx */ > > - { > > - int op1; > > - op1 = op & 7; > > - > > - switch(op >> 4) { > > - case 0: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - gen_helper_flds_FT0(cpu_env, s->tmp2_i32); > > - break; > > - case 1: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); > > - break; > > - case 2: > > - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, > > - s->mem_index, MO_LEQ); > > - gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); > > - break; > > - case 3: > > - default: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LESW); > > - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); > > - break; > > - } > > - > > - gen_helper_fp_arith_ST0_FT0(op1); > > - if (op1 == 3) { > > - /* fcomp needs pop */ > > - gen_helper_fpop(cpu_env); > > - } > > - } > > + { > > + if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { > > + /* if CR0.EM or CR0.TS are set, generate an FPU exception */ > > + /* XXX: what to do if illegal op ? */ > > + gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); > > break; > > - case 0x08: /* flds */ > > - case 0x0a: /* fsts */ > > - case 0x0b: /* fstps */ > > - case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ > > - case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ > > - case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ > > - switch(op & 7) { > > - case 0: > > - switch(op >> 4) { > > - case 0: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - gen_helper_flds_ST0(cpu_env, s->tmp2_i32); > > - break; > > - case 1: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); > > - break; > > - case 2: > > - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, > > - s->mem_index, MO_LEQ); > > - gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); > > - break; > > - case 3: > > - default: > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LESW); > > - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); > > - break; > > - } > > - break; > > - case 1: > > - /* XXX: the corresponding CPUID bit must be tested ! */ > > - switch(op >> 4) { > > - case 1: > > - gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - break; > > - case 2: > > - gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); > > - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, > > - s->mem_index, MO_LEQ); > > - break; > > - case 3: > > - default: > > - gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUW); > > - break; > > - } > > - gen_helper_fpop(cpu_env); > > - break; > > - default: > > - switch(op >> 4) { > > - case 0: > > - gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - break; > > - case 1: > > - gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUL); > > - break; > > - case 2: > > - gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); > > - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, > > - s->mem_index, MO_LEQ); > > - break; > > - case 3: > > - default: > > - gen_helper_fist_ST0(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUW); > > - break; > > - } > > - if ((op & 7) == 3) > > - gen_helper_fpop(cpu_env); > > - break; > > - } > > - break; > > - case 0x0c: /* fldenv mem */ > > - gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); > > - break; > > - case 0x0d: /* fldcw mem */ > > - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUW); > > - gen_helper_fldcw(cpu_env, s->tmp2_i32); > > - break; > > - case 0x0e: /* fnstenv mem */ > > - gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); > > - break; > > - case 0x0f: /* fnstcw mem */ > > - gen_helper_fnstcw(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUW); > > - break; > > - case 0x1d: /* fldt mem */ > > - gen_helper_fldt_ST0(cpu_env, s->A0); > > - break; > > - case 0x1f: /* fstpt mem */ > > - gen_helper_fstt_ST0(cpu_env, s->A0); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x2c: /* frstor mem */ > > - gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); > > - break; > > - case 0x2e: /* fnsave mem */ > > - gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); > > - break; > > - case 0x2f: /* fnstsw mem */ > > - gen_helper_fnstsw(s->tmp2_i32, cpu_env); > > - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > - s->mem_index, MO_LEUW); > > - break; > > - case 0x3c: /* fbld */ > > - gen_helper_fbld_ST0(cpu_env, s->A0); > > - break; > > - case 0x3e: /* fbstp */ > > - gen_helper_fbst_ST0(cpu_env, s->A0); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x3d: /* fildll */ > > - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); > > - gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); > > - break; > > - case 0x3f: /* fistpll */ > > - gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); > > - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); > > - gen_helper_fpop(cpu_env); > > - break; > > - default: > > - goto unknown_op; > > } > > - } else { > > - /* register float ops */ > > - opreg = rm; > > + modrm = x86_ldub_code(env, s); > > + mod = (modrm >> 6) & 3; > > + rm = modrm & 7; > > + op = ((b & 7) << 3) | ((modrm >> 3) & 7); > > + if (mod != 3) { > > + /* memory op */ > > + gen_lea_modrm(env, s, modrm); > > + switch (op) { > > + case 0x00 ... 0x07: /* fxxxs */ > > + case 0x10 ... 0x17: /* fixxxl */ > > + case 0x20 ... 0x27: /* fxxxl */ > > + case 0x30 ... 0x37: /* fixxx */ > > + { > > + int op1; > > + op1 = op & 7; > > > > - switch(op) { > > - case 0x08: /* fld sti */ > > - gen_helper_fpush(cpu_env); > > - gen_helper_fmov_ST0_STN(cpu_env, > > - tcg_const_i32((opreg + 1) & 7)); > > - break; > > - case 0x09: /* fxchg sti */ > > - case 0x29: /* fxchg4 sti, undocumented op */ > > - case 0x39: /* fxchg7 sti, undocumented op */ > > - gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); > > - break; > > - case 0x0a: /* grp d9/2 */ > > - switch(rm) { > > - case 0: /* fnop */ > > - /* check exceptions (FreeBSD FPU probe) */ > > - gen_helper_fwait(cpu_env); > > - break; > > - default: > > - goto unknown_op; > > - } > > - break; > > - case 0x0c: /* grp d9/4 */ > > - switch(rm) { > > - case 0: /* fchs */ > > - gen_helper_fchs_ST0(cpu_env); > > - break; > > - case 1: /* fabs */ > > - gen_helper_fabs_ST0(cpu_env); > > - break; > > - case 4: /* ftst */ > > - gen_helper_fldz_FT0(cpu_env); > > - gen_helper_fcom_ST0_FT0(cpu_env); > > - break; > > - case 5: /* fxam */ > > - gen_helper_fxam_ST0(cpu_env); > > - break; > > - default: > > - goto unknown_op; > > - } > > - break; > > - case 0x0d: /* grp d9/5 */ > > - { > > - switch(rm) { > > - case 0: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fld1_ST0(cpu_env); > > - break; > > - case 1: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldl2t_ST0(cpu_env); > > - break; > > - case 2: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldl2e_ST0(cpu_env); > > - break; > > - case 3: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldpi_ST0(cpu_env); > > - break; > > - case 4: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldlg2_ST0(cpu_env); > > - break; > > - case 5: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldln2_ST0(cpu_env); > > - break; > > - case 6: > > - gen_helper_fpush(cpu_env); > > - gen_helper_fldz_ST0(cpu_env); > > - break; > > - default: > > - goto unknown_op; > > - } > > - } > > - break; > > - case 0x0e: /* grp d9/6 */ > > - switch(rm) { > > - case 0: /* f2xm1 */ > > - gen_helper_f2xm1(cpu_env); > > - break; > > - case 1: /* fyl2x */ > > - gen_helper_fyl2x(cpu_env); > > - break; > > - case 2: /* fptan */ > > - gen_helper_fptan(cpu_env); > > - break; > > - case 3: /* fpatan */ > > - gen_helper_fpatan(cpu_env); > > - break; > > - case 4: /* fxtract */ > > - gen_helper_fxtract(cpu_env); > > - break; > > - case 5: /* fprem1 */ > > - gen_helper_fprem1(cpu_env); > > - break; > > - case 6: /* fdecstp */ > > - gen_helper_fdecstp(cpu_env); > > - break; > > - default: > > - case 7: /* fincstp */ > > - gen_helper_fincstp(cpu_env); > > - break; > > - } > > - break; > > - case 0x0f: /* grp d9/7 */ > > - switch(rm) { > > - case 0: /* fprem */ > > - gen_helper_fprem(cpu_env); > > - break; > > - case 1: /* fyl2xp1 */ > > - gen_helper_fyl2xp1(cpu_env); > > - break; > > - case 2: /* fsqrt */ > > - gen_helper_fsqrt(cpu_env); > > - break; > > - case 3: /* fsincos */ > > - gen_helper_fsincos(cpu_env); > > - break; > > - case 5: /* fscale */ > > - gen_helper_fscale(cpu_env); > > - break; > > - case 4: /* frndint */ > > - gen_helper_frndint(cpu_env); > > - break; > > - case 6: /* fsin */ > > - gen_helper_fsin(cpu_env); > > - break; > > - default: > > - case 7: /* fcos */ > > - gen_helper_fcos(cpu_env); > > - break; > > - } > > - break; > > - case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ > > - case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ > > - case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ > > - { > > - int op1; > > + switch (op >> 4) { > > + case 0: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + gen_helper_flds_FT0(cpu_env, s->tmp2_i32); > > + break; > > + case 1: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); > > + break; > > + case 2: > > + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); > > + break; > > + case 3: > > + default: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LESW); > > + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); > > + break; > > + } > > > > - op1 = op & 7; > > - if (op >= 0x20) { > > - gen_helper_fp_arith_STN_ST0(op1, opreg); > > - if (op >= 0x30) > > - gen_helper_fpop(cpu_env); > > - } else { > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > gen_helper_fp_arith_ST0_FT0(op1); > > + if (op1 == 3) { > > + /* fcomp needs pop */ > > + gen_helper_fpop(cpu_env); > > + } > > } > > - } > > - break; > > - case 0x02: /* fcom */ > > - case 0x22: /* fcom2, undocumented op */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fcom_ST0_FT0(cpu_env); > > - break; > > - case 0x03: /* fcomp */ > > - case 0x23: /* fcomp3, undocumented op */ > > - case 0x32: /* fcomp5, undocumented op */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fcom_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x15: /* da/5 */ > > - switch(rm) { > > - case 1: /* fucompp */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); > > - gen_helper_fucom_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > - gen_helper_fpop(cpu_env); > > break; > > - default: > > - goto unknown_op; > > - } > > - break; > > - case 0x1c: > > - switch(rm) { > > - case 0: /* feni (287 only, just do nop here) */ > > + case 0x08: /* flds */ > > + case 0x0a: /* fsts */ > > + case 0x0b: /* fstps */ > > + case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ > > + case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ > > + case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ > > + switch (op & 7) { > > + case 0: > > + switch (op >> 4) { > > + case 0: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + gen_helper_flds_ST0(cpu_env, s->tmp2_i32); > > + break; > > + case 1: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); > > + break; > > + case 2: > > + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); > > + break; > > + case 3: > > + default: > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LESW); > > + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); > > + break; > > + } > > + break; > > + case 1: > > + /* XXX: the corresponding CPUID bit must be tested ! */ > > + switch (op >> 4) { > > + case 1: > > + gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + break; > > + case 2: > > + gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); > > + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + break; > > + case 3: > > + default: > > + gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUW); > > + break; > > + } > > + gen_helper_fpop(cpu_env); > > + break; > > + default: > > + switch (op >> 4) { > > + case 0: > > + gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + break; > > + case 1: > > + gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUL); > > + break; > > + case 2: > > + gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); > > + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + break; > > + case 3: > > + default: > > + gen_helper_fist_ST0(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUW); > > + break; > > + } > > + if ((op & 7) == 3) { > > + gen_helper_fpop(cpu_env); > > + } > > + break; > > + } > > break; > > - case 1: /* fdisi (287 only, just do nop here) */ > > + case 0x0c: /* fldenv mem */ > > + gen_helper_fldenv(cpu_env, s->A0, > > + tcg_const_i32(dflag - 1)); > > break; > > - case 2: /* fclex */ > > - gen_helper_fclex(cpu_env); > > + case 0x0d: /* fldcw mem */ > > + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUW); > > + gen_helper_fldcw(cpu_env, s->tmp2_i32); > > break; > > - case 3: /* fninit */ > > - gen_helper_fninit(cpu_env); > > + case 0x0e: /* fnstenv mem */ > > + gen_helper_fstenv(cpu_env, s->A0, > > + tcg_const_i32(dflag - 1)); > > break; > > - case 4: /* fsetpm (287 only, just do nop here) */ > > + case 0x0f: /* fnstcw mem */ > > + gen_helper_fnstcw(s->tmp2_i32, cpu_env); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUW); > > break; > > - default: > > - goto unknown_op; > > - } > > - break; > > - case 0x1d: /* fucomi */ > > - if (!(s->cpuid_features & CPUID_CMOV)) { > > - goto illegal_op; > > - } > > - gen_update_cc_op(s); > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fucomi_ST0_FT0(cpu_env); > > - set_cc_op(s, CC_OP_EFLAGS); > > - break; > > - case 0x1e: /* fcomi */ > > - if (!(s->cpuid_features & CPUID_CMOV)) { > > - goto illegal_op; > > - } > > - gen_update_cc_op(s); > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fcomi_ST0_FT0(cpu_env); > > - set_cc_op(s, CC_OP_EFLAGS); > > - break; > > - case 0x28: /* ffree sti */ > > - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); > > - break; > > - case 0x2a: /* fst sti */ > > - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); > > - break; > > - case 0x2b: /* fstp sti */ > > - case 0x0b: /* fstp1 sti, undocumented op */ > > - case 0x3a: /* fstp8 sti, undocumented op */ > > - case 0x3b: /* fstp9 sti, undocumented op */ > > - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x2c: /* fucom st(i) */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fucom_ST0_FT0(cpu_env); > > - break; > > - case 0x2d: /* fucomp st(i) */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fucom_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x33: /* de/3 */ > > - switch(rm) { > > - case 1: /* fcompp */ > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); > > - gen_helper_fcom_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > + case 0x1d: /* fldt mem */ > > + gen_helper_fldt_ST0(cpu_env, s->A0); > > + break; > > + case 0x1f: /* fstpt mem */ > > + gen_helper_fstt_ST0(cpu_env, s->A0); > > gen_helper_fpop(cpu_env); > > break; > > - default: > > - goto unknown_op; > > - } > > - break; > > - case 0x38: /* ffreep sti, undocumented op */ > > - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fpop(cpu_env); > > - break; > > - case 0x3c: /* df/4 */ > > - switch(rm) { > > - case 0: > > + case 0x2c: /* frstor mem */ > > + gen_helper_frstor(cpu_env, s->A0, > > + tcg_const_i32(dflag - 1)); > > + break; > > + case 0x2e: /* fnsave mem */ > > + gen_helper_fsave(cpu_env, s->A0, > > + tcg_const_i32(dflag - 1)); > > + break; > > + case 0x2f: /* fnstsw mem */ > > gen_helper_fnstsw(s->tmp2_i32, cpu_env); > > - tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); > > - gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); > > + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, > > + s->mem_index, MO_LEUW); > > + break; > > + case 0x3c: /* fbld */ > > + gen_helper_fbld_ST0(cpu_env, s->A0); > > + break; > > + case 0x3e: /* fbstp */ > > + gen_helper_fbst_ST0(cpu_env, s->A0); > > + gen_helper_fpop(cpu_env); > > + break; > > + case 0x3d: /* fildll */ > > + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); > > + break; > > + case 0x3f: /* fistpll */ > > + gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); > > + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, > > + s->mem_index, MO_LEQ); > > + gen_helper_fpop(cpu_env); > > break; > > default: > > goto unknown_op; > > } > > - break; > > - case 0x3d: /* fucomip */ > > - if (!(s->cpuid_features & CPUID_CMOV)) { > > - goto illegal_op; > > - } > > - gen_update_cc_op(s); > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fucomi_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > - set_cc_op(s, CC_OP_EFLAGS); > > - break; > > - case 0x3e: /* fcomip */ > > - if (!(s->cpuid_features & CPUID_CMOV)) { > > - goto illegal_op; > > - } > > - gen_update_cc_op(s); > > - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_helper_fcomi_ST0_FT0(cpu_env); > > - gen_helper_fpop(cpu_env); > > - set_cc_op(s, CC_OP_EFLAGS); > > - break; > > - case 0x10 ... 0x13: /* fcmovxx */ > > - case 0x18 ... 0x1b: > > - { > > - int op1; > > - TCGLabel *l1; > > - static const uint8_t fcmov_cc[8] = { > > - (JCC_B << 1), > > - (JCC_Z << 1), > > - (JCC_BE << 1), > > - (JCC_P << 1), > > - }; > > + } else { > > + /* register float ops */ > > + opreg = rm; > > + > > + switch (op) { > > + case 0x08: /* fld sti */ > > + gen_helper_fpush(cpu_env); > > + gen_helper_fmov_ST0_STN(cpu_env, > > + tcg_const_i32((opreg + 1) & 7)); > > + break; > > + case 0x09: /* fxchg sti */ > > + case 0x29: /* fxchg4 sti, undocumented op */ > > + case 0x39: /* fxchg7 sti, undocumented op */ > > + gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); > > + break; > > + case 0x0a: /* grp d9/2 */ > > + switch (rm) { > > + case 0: /* fnop */ > > + /* check exceptions (FreeBSD FPU probe) */ > > + gen_helper_fwait(cpu_env); > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x0c: /* grp d9/4 */ > > + switch (rm) { > > + case 0: /* fchs */ > > + gen_helper_fchs_ST0(cpu_env); > > + break; > > + case 1: /* fabs */ > > + gen_helper_fabs_ST0(cpu_env); > > + break; > > + case 4: /* ftst */ > > + gen_helper_fldz_FT0(cpu_env); > > + gen_helper_fcom_ST0_FT0(cpu_env); > > + break; > > + case 5: /* fxam */ > > + gen_helper_fxam_ST0(cpu_env); > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x0d: /* grp d9/5 */ > > + { > > + switch (rm) { > > + case 0: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fld1_ST0(cpu_env); > > + break; > > + case 1: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldl2t_ST0(cpu_env); > > + break; > > + case 2: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldl2e_ST0(cpu_env); > > + break; > > + case 3: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldpi_ST0(cpu_env); > > + break; > > + case 4: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldlg2_ST0(cpu_env); > > + break; > > + case 5: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldln2_ST0(cpu_env); > > + break; > > + case 6: > > + gen_helper_fpush(cpu_env); > > + gen_helper_fldz_ST0(cpu_env); > > + break; > > + default: > > + goto unknown_op; > > + } > > + } > > + break; > > + case 0x0e: /* grp d9/6 */ > > + switch (rm) { > > + case 0: /* f2xm1 */ > > + gen_helper_f2xm1(cpu_env); > > + break; > > + case 1: /* fyl2x */ > > + gen_helper_fyl2x(cpu_env); > > + break; > > + case 2: /* fptan */ > > + gen_helper_fptan(cpu_env); > > + break; > > + case 3: /* fpatan */ > > + gen_helper_fpatan(cpu_env); > > + break; > > + case 4: /* fxtract */ > > + gen_helper_fxtract(cpu_env); > > + break; > > + case 5: /* fprem1 */ > > + gen_helper_fprem1(cpu_env); > > + break; > > + case 6: /* fdecstp */ > > + gen_helper_fdecstp(cpu_env); > > + break; > > + default: > > + case 7: /* fincstp */ > > + gen_helper_fincstp(cpu_env); > > + break; > > + } > > + break; > > + case 0x0f: /* grp d9/7 */ > > + switch (rm) { > > + case 0: /* fprem */ > > + gen_helper_fprem(cpu_env); > > + break; > > + case 1: /* fyl2xp1 */ > > + gen_helper_fyl2xp1(cpu_env); > > + break; > > + case 2: /* fsqrt */ > > + gen_helper_fsqrt(cpu_env); > > + break; > > + case 3: /* fsincos */ > > + gen_helper_fsincos(cpu_env); > > + break; > > + case 5: /* fscale */ > > + gen_helper_fscale(cpu_env); > > + break; > > + case 4: /* frndint */ > > + gen_helper_frndint(cpu_env); > > + break; > > + case 6: /* fsin */ > > + gen_helper_fsin(cpu_env); > > + break; > > + default: > > + case 7: /* fcos */ > > + gen_helper_fcos(cpu_env); > > + break; > > + } > > + break; > > + case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ > > + case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ > > + case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ > > + { > > + int op1; > > > > + op1 = op & 7; > > + if (op >= 0x20) { > > + gen_helper_fp_arith_STN_ST0(op1, opreg); > > + if (op >= 0x30) { > > + gen_helper_fpop(cpu_env); > > + } > > + } else { > > + gen_helper_fmov_FT0_STN(cpu_env, > > + tcg_const_i32(opreg)); > > + gen_helper_fp_arith_ST0_FT0(op1); > > + } > > + } > > + break; > > + case 0x02: /* fcom */ > > + case 0x22: /* fcom2, undocumented op */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fcom_ST0_FT0(cpu_env); > > + break; > > + case 0x03: /* fcomp */ > > + case 0x23: /* fcomp3, undocumented op */ > > + case 0x32: /* fcomp5, undocumented op */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fcom_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + break; > > + case 0x15: /* da/5 */ > > + switch (rm) { > > + case 1: /* fucompp */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); > > + gen_helper_fucom_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + gen_helper_fpop(cpu_env); > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x1c: > > + switch (rm) { > > + case 0: /* feni (287 only, just do nop here) */ > > + break; > > + case 1: /* fdisi (287 only, just do nop here) */ > > + break; > > + case 2: /* fclex */ > > + gen_helper_fclex(cpu_env); > > + break; > > + case 3: /* fninit */ > > + gen_helper_fninit(cpu_env); > > + break; > > + case 4: /* fsetpm (287 only, just do nop here) */ > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x1d: /* fucomi */ > > if (!(s->cpuid_features & CPUID_CMOV)) { > > goto illegal_op; > > } > > - op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); > > - l1 = gen_new_label(); > > - gen_jcc1_noeob(s, op1, l1); > > - gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); > > - gen_set_label(l1); > > + gen_update_cc_op(s); > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fucomi_ST0_FT0(cpu_env); > > + set_cc_op(s, CC_OP_EFLAGS); > > + break; > > + case 0x1e: /* fcomi */ > > + if (!(s->cpuid_features & CPUID_CMOV)) { > > + goto illegal_op; > > + } > > + gen_update_cc_op(s); > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fcomi_ST0_FT0(cpu_env); > > + set_cc_op(s, CC_OP_EFLAGS); > > + break; > > + case 0x28: /* ffree sti */ > > + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); > > + break; > > + case 0x2a: /* fst sti */ > > + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); > > + break; > > + case 0x2b: /* fstp sti */ > > + case 0x0b: /* fstp1 sti, undocumented op */ > > + case 0x3a: /* fstp8 sti, undocumented op */ > > + case 0x3b: /* fstp9 sti, undocumented op */ > > + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fpop(cpu_env); > > + break; > > + case 0x2c: /* fucom st(i) */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fucom_ST0_FT0(cpu_env); > > + break; > > + case 0x2d: /* fucomp st(i) */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fucom_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + break; > > + case 0x33: /* de/3 */ > > + switch (rm) { > > + case 1: /* fcompp */ > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); > > + gen_helper_fcom_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + gen_helper_fpop(cpu_env); > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x38: /* ffreep sti, undocumented op */ > > + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fpop(cpu_env); > > + break; > > + case 0x3c: /* df/4 */ > > + switch (rm) { > > + case 0: > > + gen_helper_fnstsw(s->tmp2_i32, cpu_env); > > + tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); > > + gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); > > + break; > > + default: > > + goto unknown_op; > > + } > > + break; > > + case 0x3d: /* fucomip */ > > + if (!(s->cpuid_features & CPUID_CMOV)) { > > + goto illegal_op; > > + } > > + gen_update_cc_op(s); > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fucomi_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + set_cc_op(s, CC_OP_EFLAGS); > > + break; > > + case 0x3e: /* fcomip */ > > + if (!(s->cpuid_features & CPUID_CMOV)) { > > + goto illegal_op; > > + } > > + gen_update_cc_op(s); > > + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_helper_fcomi_ST0_FT0(cpu_env); > > + gen_helper_fpop(cpu_env); > > + set_cc_op(s, CC_OP_EFLAGS); > > + break; > > + case 0x10 ... 0x13: /* fcmovxx */ > > + case 0x18 ... 0x1b: > > + { > > + int op1; > > + TCGLabel *l1; > > + static const uint8_t fcmov_cc[8] = { > > + (JCC_B << 1), > > + (JCC_Z << 1), > > + (JCC_BE << 1), > > + (JCC_P << 1), > > + }; > > + > > + if (!(s->cpuid_features & CPUID_CMOV)) { > > + goto illegal_op; > > + } > > + op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); > > + l1 = gen_new_label(); > > + gen_jcc1_noeob(s, op1, l1); > > + gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); > > + gen_set_label(l1); > > + } > > + break; > > + default: > > + goto unknown_op; > > } > > - break; > > - default: > > - goto unknown_op; > > } > > } > > break; > > -- > > 2.25.1 > >