[PATCH 00/24] kbl and gen9 workarounds v2

[PATCH 00/24] kbl and gen9 workarounds v2

[Mika Kuoppala]

WaKVMNotificationOnConfigChange was not for skl/bxt even tho
the documentation claims so.

Addressed Arun's comment about littering the generic gen
workaround function with revid checks.

Fbc ones have a names also as Ville pointed out.

Added one patch to extend one skl workaround.

-Mika

Mika Kuoppala (24):
  drm/i915/kbl: Init gen9 workarounds
  drm/i915/kbl: Add REVID macro
  drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
  drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
  drm/i915: Mimic skl with WaForceEnableNonCoherent
  drm/i915/kbl: Add WaEnableGapsTsvCreditFix
  drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
  drm/i915/kbl: Add WaDisableSDEUnitClockGating
  drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
  drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
  drm/i915/gen9: Enable must set chicken bits in config0 reg
  drm/i915/kbl: Add WaDisableGamClockGating
  drm/i915/kbl: Add WaDisableDynamicCreditSharing
  drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
  drm/i915/gen9: Add WaDisableSkipCaching
  drm/i915/skl: Add WAC6entrylatency
  drm/i915/kbl: Add WaForGAMHang
  drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
  drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
  drm/i915/gen9: Add WaEnableChickenDCPR
  drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
  drm/i915/gen9: Add WaFbcWakeMemOn
  drm/i195/fbc: Add WaFbcNukeOnHostModify
  drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

 drivers/gpu/drm/i915/i915_drv.h         |   9 ++
 drivers/gpu/drm/i915/i915_gem_stolen.c  |   6 +-
 drivers/gpu/drm/i915/i915_reg.h         |  20 +++++
 drivers/gpu/drm/i915/intel_lrc.c        |  57 ++++++++++++-
 drivers/gpu/drm/i915/intel_mocs.c       |  10 +++
 drivers/gpu/drm/i915/intel_pm.c         |  68 +++++++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 146 +++++++++++++++++++++++---------
 7 files changed, 263 insertions(+), 53 deletions(-)

-- 
2.5.0

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[PATCH 01/24] drm/i915/kbl: Init gen9 workarounds

[Mika Kuoppala]

Kabylake is part of gen9 family so init the generic gen9
workarounds for it.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a3978f9b..f52105531877 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -911,21 +911,21 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	uint32_t tmp;
 	int ret;
 
-	/* WaEnableLbsSlaRetryTimerDecrement:skl */
+	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 
-	/* WaDisableKillLogic:bxt,skl */
+	/* WaDisableKillLogic:bxt,skl,kbl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
 
-	/* WaClearFlowControlGpgpuContextSave:skl,bxt */
-	/* WaDisablePartialInstShootdown:skl,bxt */
+	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
+	/* WaDisablePartialInstShootdown:skl,bxt,kbl */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  FLOW_CONTROL_ENABLE |
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics:skl,bxt */
+	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
@@ -947,18 +947,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		 */
 	}
 
-	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
-	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
+	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
+	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 			  GEN9_ENABLE_YV12_BUGFIX |
 			  GEN9_ENABLE_GPGPU_PREEMPTION);
 
-	/* Wa4x4STCOptimizationDisable:skl,bxt */
-	/* WaDisablePartialResolveInVc:skl,bxt */
+	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
+	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
-	/* WaCcsTlbPrefetchDisable:skl,bxt */
+	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
@@ -975,24 +975,26 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
-	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
-	if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
+	if (IS_SKYLAKE(dev_priv) ||
+	    IS_KABYLAKE(dev_priv) ||
+	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
-	/* WaDisableSTUnitPowerOptimization:skl,bxt */
+	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-	/* WaOCLCoherentLineFlush:skl,bxt */
+	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
+	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
 	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 	if (ret)
 		return ret;
 
-	/* WaAllowUMDToModifyHDCChicken1:skl,bxt */
+	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 	if (ret)
 		return ret;
@@ -1174,6 +1176,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int kbl_init_workarounds(struct intel_engine_cs *engine)
+{
+	int ret;
+
+	ret = gen9_init_workarounds(engine);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -1195,6 +1208,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
 	if (IS_BROXTON(dev_priv))
 		return bxt_init_workarounds(engine);
 
+	if (IS_KABYLAKE(dev_priv))
+		return kbl_init_workarounds(engine);
+
 	return 0;
 }
 
-- 
2.5.0

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[PATCH 02/24] drm/i915/kbl: Add REVID macro

[Mika Kuoppala]

Add REVID macro for kbl to limit wa applicability to particular
revision range.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4c8e341655c..98cb1f178e3e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2715,6 +2715,12 @@ struct drm_i915_cmd_table {
 
 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
 
+#define KBL_REVID_A0		0x0
+#define KBL_REVID_B0		0x1
+
+#define IS_KBL_REVID(p, since, until) \
+	(IS_KABYLAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
-- 
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[PATCH 03/24] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0

[Mika Kuoppala]

We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.

References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_stolen.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f9253f2b7ba0..e9cd82290408 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -55,8 +55,10 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
 		return -ENODEV;
 
 	/* See the comment at the drm_mm_init() call for more about this check.
-	 * WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
-	if (IS_GEN8(dev_priv) && start < 4096)
+	 * WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)
+	 */
+	if (start < 4096 && (IS_GEN8(dev_priv) ||
+			     IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
 		start = 4096;
 
 	mutex_lock(&dev_priv->mm.stolen_lock);
-- 
2.5.0

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[PATCH 04/24] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent

[Mika Kuoppala]

The revision id range for this workaround has changed. So apply
it to all revids on all gen9.

References: HSD#2134449
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f52105531877..47557bd34945 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -908,7 +908,6 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	uint32_t tmp;
 	int ret;
 
 	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
@@ -968,12 +967,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
-	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-	if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
-	    IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
-		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
+			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 
 	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
 	if (IS_SKYLAKE(dev_priv) ||
-- 
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[PATCH 05/24] drm/i915: Mimic skl with WaForceEnableNonCoherent

[Mika Kuoppala]

Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("drm/i915/skl: Fix spurious gpu hang with gt3/gt4
revs"). In this scope consider kbl to be skl with a bigger revision than
E0 so play it safe and bind these two workarounds to the
WaForceContextSaveRestoreNonCoherent, and apply to all gen9.

References: HSD#2134449, HSD#2131413
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47557bd34945..91d5d093f3cb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -972,6 +972,27 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 
+	/* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
+	 * both tied to WaForceContextSaveRestoreNonCoherent
+	 * in some hsds for skl. We keep the tie for all gen9. The
+	 * documentation is a bit hazy and so we want to get common behaviour,
+	 * even tho there is no clear evidence we would need both on kbl/bxt.
+	 * This area has been source of system hangs so we play it safe
+	 * and mimic the skl regarless of what bspec says.
+	 *
+	 * Use Force Non-Coherent whenever executing a 3D context. This
+	 * is a workaround for a possible hang in the unlikely event
+	 * a TLB invalidation occurs during a PSD flush.
+	 */
+
+	/* WaForceEnableNonCoherent:skl,bxt,kbl */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_NON_COHERENT);
+
+	/* WaDisableHDCInvalidation:skl,bxt,kbl */
+	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+		   BDW_DISABLE_HDC_INVALIDATION);
+
 	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
 	if (IS_SKYLAKE(dev_priv) ||
 	    IS_KABYLAKE(dev_priv) ||
@@ -1084,22 +1105,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
-	/* This is tied to WaForceContextSaveRestoreNonCoherent */
-	if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
-		/*
-		 *Use Force Non-Coherent whenever executing a 3D context. This
-		 * is a workaround for a possible hang in the unlikely event
-		 * a TLB invalidation occurs during a PSD flush.
-		 */
-		/* WaForceEnableNonCoherent:skl */
-		WA_SET_BIT_MASKED(HDC_CHICKEN0,
-				  HDC_FORCE_NON_COHERENT);
-
-		/* WaDisableHDCInvalidation:skl */
-		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-			   BDW_DISABLE_HDC_INVALIDATION);
-	}
-
 	/* WaBarrierPerformanceFixDisable:skl */
 	if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
-- 
2.5.0

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[PATCH 06/24] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

[Mika Kuoppala]

We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.

v2: Don't add revid checks to gen9 init workarounds (Arun)

References: HSD#2126660
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 91d5d093f3cb..c4232009b4a2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1180,12 +1180,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 
 static int kbl_init_workarounds(struct intel_engine_cs *engine)
 {
+	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
 	ret = gen9_init_workarounds(engine);
 	if (ret)
 		return ret;
 
+	/* WaEnableGapsTsvCreditFix:kbl */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN9_GAPS_TSV_CREDIT_DISABLE));
+
 	return 0;
 }
 
-- 
2.5.0

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[PATCH 07/24] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

[Mika Kuoppala]

Add this workaround for kbl revid A0 only.

v2: rebase

References: HSD#1911714
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c |  5 +++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1afaaf..c5e0094d0e75 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1260,6 +1260,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 		return ret;
 	index = ret;
 
+	/* WaClearSlmSpaceAtContextSwitch:kbl */
+	/* Actual scratch location is at 128 bytes offset */
+	if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+		uint32_t scratch_addr
+			= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
+
+		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
+		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
+					   PIPE_CONTROL_GLOBAL_GTT_IVB |
+					   PIPE_CONTROL_CS_STALL |
+					   PIPE_CONTROL_QW_WRITE));
+		wa_ctx_emit(batch, index, scratch_addr);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+	}
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
 		wa_ctx_emit(batch, index, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c4232009b4a2..3963aeea90b1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1191,6 +1191,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 				   GEN9_GAPS_TSV_CREDIT_DISABLE));
 
+	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FENCE_DEST_SLM_DISABLE);
+
 	return 0;
 }
 
-- 
2.5.0

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[PATCH 08/24] drm/i915/kbl: Add WaDisableSDEUnitClockGating

[Mika Kuoppala]

Add this workaround until upto kbl revid B0.

References: HSD#1802092
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6dfd0264950..fc34add6ab82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6849,11 +6849,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void kabylake_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
+	I915_WRITE(CHICKEN_PAR1_1,
+		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+
+	/* WaDisableSDEUnitClockGating:kbl */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+}
+
 static void skylake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 }
@@ -7319,7 +7333,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 	if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
+		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
 	else if (IS_BROXTON(dev_priv))
 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
 	else if (IS_BROADWELL(dev_priv))
-- 
2.5.0

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[PATCH 09/24] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw

[Mika Kuoppala]

According to bspec this workaround helps to reduce lag and improve
performance on edp.

Documentation suggests this for bdw and all gen9. However evidence
shows that this register is missing on gen9 and causing unclaimed mmio
access if we access it. So apply to bdw only where the reg
exists and can hold its value.

v2: drop skl

References: HSD#2134579
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e3077259541a..1f84c2ff3563 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6035,6 +6035,9 @@ enum skl_disp_power_wells {
 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
 
+#define CHICKEN_PAR2_1		_MMIO(0x42090)
+#define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fc34add6ab82..a6cb2e55afe2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6916,6 +6916,10 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
 	 */
 	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
 
+	/* WaKVMNotificationOnConfigChange:bdw */
+	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
+		   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+
 	lpt_init_clock_gating(dev);
 }
 
-- 
2.5.0

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[PATCH 10/24] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

[Mika Kuoppala]

Extend the scope of this workaround, already used in skl,
to also take effect in kbl.

References: HSD#2132677
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c        |  5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98cb1f178e3e..ffad2840b72f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2717,6 +2717,9 @@ struct drm_i915_cmd_table {
 
 #define KBL_REVID_A0		0x0
 #define KBL_REVID_B0		0x1
+#define KBL_REVID_C0		0x2
+#define KBL_REVID_D0		0x3
+#define KBL_REVID_E0		0x3
 
 #define IS_KBL_REVID(p, since, until) \
 	(IS_KABYLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c5e0094d0e75..819adbdee1c2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1081,12 +1081,13 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
 	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
 
 	/*
-	 * WaDisableLSQCROPERFforOCL:skl
+	 * WaDisableLSQCROPERFforOCL:skl,kbl
 	 * This WA is implemented in skl_init_clock_gating() but since
 	 * this batch updates GEN8_L3SQCREG4 with default value we need to
 	 * set this bit here to retain the WA during flush.
 	 */
-	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
+	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0) ||
+	    IS_KBL_REVID(engine->i915, 0, KBL_REVID_E0))
 		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
 
 	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3963aeea90b1..dd743d988b1a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1196,6 +1196,19 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
 				  HDC_FENCE_DEST_SLM_DISABLE);
 
+	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+	 * involving this register should also be added to WA batch as required.
+	 */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+		/* WaDisableLSQCROPERFforOCL:kbl */
+		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			   GEN8_LQSC_RO_PERF_DIS);
+
+	/* WaDisableLSQCROPERFforOCL:kbl */
+	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
2.5.0

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[PATCH 11/24] drm/i915/gen9: Enable must set chicken bits in config0 reg

[Mika Kuoppala]

The bspec states that these must be set in CONFIG0 for all gen9.

v2: rebase

References: HSD#2134995
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++----------
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1f84c2ff3563..5cba851370ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
 #define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
 
+#define GEN8_CONFIG0			_MMIO(0xD00)
+#define  GEN9_DEFAULT_FIXES		(1<<3 | 1<<2 | 1 << 1)
+
 #define GAC_ECO_BITS			_MMIO(0x14090)
 #define   ECOBITS_SNB_BIT		(1<<13)
 #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6cb2e55afe2..f1ddc8310fe6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -54,14 +54,24 @@
 #define INTEL_RC6p_ENABLE			(1<<1)
 #define INTEL_RC6pp_ENABLE			(1<<2)
 
-static void bxt_init_clock_gating(struct drm_device *dev)
+static void gen9_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
+	I915_WRITE(GEN8_CONFIG0,
+		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+}
+
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	gen9_init_clock_gating(dev);
+
 	/* WaDisableSDEUnitClockGating:bxt */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -6853,9 +6863,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+	gen9_init_clock_gating(dev);
 
 	/* WaDisableSDEUnitClockGating:kbl */
 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
@@ -6865,11 +6873,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 
 static void skylake_init_clock_gating(struct drm_device *dev)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
-	I915_WRITE(CHICKEN_PAR1_1,
-		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+	gen9_init_clock_gating(dev);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 12/24] drm/i915/kbl: Add WaDisableGamClockGating

[Mika Kuoppala]

According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.

References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cba851370ec..14e0ec818ea4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6937,6 +6937,7 @@ enum skl_disp_power_wells {
 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
+# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f1ddc8310fe6..6cb450917867 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6869,6 +6869,11 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableGamClockGating:kbl */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void skylake_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 13/24] drm/i915/kbl: Add WaDisableDynamicCreditSharing

[Mika Kuoppala]

Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.

References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 14e0ec818ea4..e0441da08201 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1672,6 +1672,8 @@ enum skl_disp_power_wells {
 
 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
 
+#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
+
 #if 0
 #define PRB0_TAIL	_MMIO(0x2030)
 #define PRB0_HEAD	_MMIO(0x2034)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dd743d988b1a..64a2dc47443d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1191,6 +1191,10 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 				   GEN9_GAPS_TSV_CREDIT_DISABLE));
 
+	/* WaDisableDynamicCreditSharing:kbl */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+		WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28));
+
 	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
 	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
-- 
2.5.0

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[PATCH 14/24] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl

[Mika Kuoppala]

Add this workaround for both bxt and kbl up to until
rev B0.

References: HSD#2136703
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0441da08201..ec31eca06807 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6087,6 +6087,7 @@ enum skl_disp_power_wells {
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
 # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
 #define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
+# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 64a2dc47443d..a1488712628b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1175,6 +1175,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 		I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
 					   L3_HIGH_PRIO_CREDITS(2));
 
+	/* WaInsertDummyPushConstPs:bxt */
+	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
 	return 0;
 }
 
@@ -1208,6 +1213,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
 			   GEN8_LQSC_RO_PERF_DIS);
 
+	/* WaInsertDummyPushConstPs:kbl */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
 	/* WaDisableLSQCROPERFforOCL:kbl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
-- 
2.5.0

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[PATCH 15/24] drm/i915/gen9: Add WaDisableSkipCaching

[Mika Kuoppala]

Make sure that we never enable skip caching on gen9 by
accident.

References: HSD#2134698
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index b765c75f3fcd..8f96c40e415c 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -156,6 +156,16 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
+	/* WaDisableSkipCaching:skl,bxt,kbl */
+	if (IS_GEN9(dev_priv)) {
+		int i;
+
+		for (i = 0; i < table->size; i++)
+			if (WARN_ON(table->table[i].l3cc_value &
+				    (L3_ESC(1) || L3_SCC(0x7))))
+				return false;
+	}
+
 	return result;
 }
 
-- 
2.5.0

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[PATCH 16/24] drm/i915/skl: Add WAC6entrylatency

[Mika Kuoppala]

This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.

v2: rebase

References: HSD#4712857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec31eca06807..77f5edc5f915 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2166,6 +2166,9 @@ enum skl_disp_power_wells {
 
 #define FBC_LL_SIZE		(1536)
 
+#define FBC_LLC_READ_CTRL	_MMIO(0x9044)
+#define   FBC_LLC_FULLY_OPEN	(1<<30)
+
 /* Framebuffer compression for GM45+ */
 #define DPFC_CB_BASE		_MMIO(0x3200)
 #define DPFC_CONTROL		_MMIO(0x3208)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6cb450917867..d3ad26be69dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6878,7 +6878,13 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 
 static void skylake_init_clock_gating(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	gen9_init_clock_gating(dev);
+
+	/* WAC6entrylatency:skl */
+	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+		   FBC_LLC_FULLY_OPEN);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 17/24] drm/i915/kbl: Add WaForGAMHang

[Mika Kuoppala]

Add this workaround for A0 and B0 revisions

References: HSD#2226935
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 819adbdee1c2..0612b6c8ffcf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1674,9 +1674,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	struct intel_ringbuffer *ringbuf = request->ringbuf;
 	struct intel_engine_cs *engine = ringbuf->engine;
 	u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
-	bool vf_flush_wa = false;
+	bool vf_flush_wa = false, dc_flush_wa = false;
 	u32 flags = 0;
 	int ret;
+	int len;
 
 	flags |= PIPE_CONTROL_CS_STALL;
 
@@ -1703,9 +1704,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 		 */
 		if (IS_GEN9(request->i915))
 			vf_flush_wa = true;
+
+		/* WaForGAMHang:kbl */
+		if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
+			dc_flush_wa = true;
 	}
 
-	ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
+	len = 6;
+
+	if (vf_flush_wa)
+		len += 6;
+
+	if (dc_flush_wa)
+		len += 12;
+
+	ret = intel_ring_begin(request, len);
 	if (ret)
 		return ret;
 
@@ -1718,12 +1731,31 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 		intel_logical_ring_emit(ringbuf, 0);
 	}
 
+	if (dc_flush_wa) {
+		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+		intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+	}
+
 	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
 	intel_logical_ring_emit(ringbuf, flags);
 	intel_logical_ring_emit(ringbuf, scratch_addr);
 	intel_logical_ring_emit(ringbuf, 0);
 	intel_logical_ring_emit(ringbuf, 0);
 	intel_logical_ring_emit(ringbuf, 0);
+
+	if (dc_flush_wa) {
+		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+		intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+		intel_logical_ring_emit(ringbuf, 0);
+	}
+
 	intel_logical_ring_advance(ringbuf);
 
 	return 0;
-- 
2.5.0

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[PATCH 18/24] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

[Mika Kuoppala]

We need this gafs bit to be enabled for hw fix to
take effect.

References: HSD#2227156, HSD#2227050
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77f5edc5f915..509238561935 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6084,6 +6084,7 @@ enum skl_disp_power_wells {
 
 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
+#define GEN8_CS_CHICKEN2		_MMIO(0x2194)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a1488712628b..b7b36c1cfdc3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1117,6 +1117,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
 			GEN7_HALF_SLICE_CHICKEN1,
 			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaDisableGafsUnitClkGating:skl */
+	WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
+
 	/* WaDisableLSQCROPERFforOCL:skl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
@@ -1218,6 +1221,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
+	/* WaDisableGafsUnitClkGating:kbl */
+	WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
+
 	/* WaDisableLSQCROPERFforOCL:kbl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
-- 
2.5.0

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[PATCH 19/24] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

[Mika Kuoppala]

This is needed for all kbl revision.

v2: Don't add revid checks to generic gen9 init (Arun)

References: HSD#2135593
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b7b36c1cfdc3..ec19fe1f914a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1224,6 +1224,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 	/* WaDisableGafsUnitClkGating:kbl */
 	WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
 
+	/* WaDisableSbeCacheDispatchPortSharing:kbl */
+	WA_SET_BIT_MASKED(
+		GEN7_HALF_SLICE_CHICKEN1,
+		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
 	/* WaDisableLSQCROPERFforOCL:kbl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
-- 
2.5.0

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[PATCH 20/24] drm/i915/gen9: Add WaEnableChickenDCPR

[Mika Kuoppala]

Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.

v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 509238561935..280d2137f90f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6066,6 +6066,9 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
+#define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
+#define   MASK_WAKEMEM			(1<<13)
+
 #define SKL_DFSM			_MMIO(0x51000)
 #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d3ad26be69dd..9ae1b0646678 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -64,6 +64,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(GEN8_CONFIG0,
 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+
+	/* WaEnableChickenDCPR:skl,bxt,kbl */
+	I915_WRITE(GEN8_CHICKEN_DCPR_1,
+		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 21/24] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

[Mika Kuoppala]

According to bspec this prevents screen corruption when fbc is
used.

v2: This workaround has a name, use it (Ville)

References: HSD#2135555, HSD#2137270, BSID#562
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ae1b0646678..b2acb82b302b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -68,6 +68,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaEnableChickenDCPR:skl,bxt,kbl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
+	I915_WRITE(DISP_ARB_CTL,
+		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
@@ -2799,7 +2803,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 
 	if (dirty & WM_DIRTY_FBC) {
 		val = I915_READ(DISP_ARB_CTL);
-		if (results->enable_fbc_wm)
+		if (!IS_GEN9(dev) && results->enable_fbc_wm)
 			val &= ~DISP_FBC_WM_DIS;
 		else
 			val |= DISP_FBC_WM_DIS;
-- 
2.5.0

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[PATCH 22/24] drm/i915/gen9: Add WaFbcWakeMemOn

[Mika Kuoppala]

Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.

v2: use correct workaround name

References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 280d2137f90f..2f3a3960f5f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2208,6 +2208,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_STATUS		_MMIO(0x43210)
 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
+#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID	(1<<0)
 #define   SNB_FBC_FRONT_BUFFER	(1<<1)
@@ -6053,6 +6054,7 @@ enum skl_disp_power_wells {
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
 
 #define DISP_ARB_CTL	_MMIO(0x45000)
+#define  DISP_FBC_MEMORY_WAKE		(1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 #define DISP_ARB_CTL2	_MMIO(0x45004)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b2acb82b302b..6d9cf487ea40 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -70,8 +70,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
 	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-	I915_WRITE(DISP_ARB_CTL,
-		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
+	/* WaFbcWakeMemOn:skl,bxt,kbl */
+	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+		   DISP_FBC_WM_DIS |
+		   DISP_FBC_MEMORY_WAKE);
+
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_DISABLE_DUMMY0);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 23/24] drm/i195/fbc: Add WaFbcNukeOnHostModify

[Mika Kuoppala]

Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.

v2: proper workaround name

References: HSD#2227109, HSDES#1404569388
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f3a3960f5f7..e08f29685b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
+#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1<<23)
 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID	(1<<0)
 #define   SNB_FBC_FRONT_BUFFER	(1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6d9cf487ea40..d4cbae4f3ce7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6887,6 +6887,10 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
 		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaFbcNukeOnHostModify:kbl */
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void skylake_init_clock_gating(struct drm_device *dev)
@@ -6898,6 +6902,10 @@ static void skylake_init_clock_gating(struct drm_device *dev)
 	/* WAC6entrylatency:skl */
 	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
 		   FBC_LLC_FULLY_OPEN);
+
+	/* WaFbcNukeOnHostModify:skl */
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 24/24] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Mika Kuoppala]

There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.

References: BSID#779
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ec19fe1f914a..a27e68a13872 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1080,7 +1080,7 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
 			   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 	}
 
-	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
+	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
 		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
 		I915_WRITE(FF_SLICE_CS_CHICKEN2,
 			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
-- 
2.5.0

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Re: [PATCH 21/24] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

[Ville Syrjälä]

On Fri, May 27, 2016 at 05:27:01PM +0300, Mika Kuoppala wrote:
> According to bspec this prevents screen corruption when fbc is
> used.
> 
> v2: This workaround has a name, use it (Ville)
> 
> References: HSD#2135555, HSD#2137270, BSID#562
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9ae1b0646678..b2acb82b302b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -68,6 +68,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  	/* WaEnableChickenDCPR:skl,bxt,kbl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> +
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> +	I915_WRITE(DISP_ARB_CTL,
> +		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
>  }
>  
>  static void bxt_init_clock_gating(struct drm_device *dev)
> @@ -2799,7 +2803,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>  
>  	if (dirty & WM_DIRTY_FBC) {
>  		val = I915_READ(DISP_ARB_CTL);
> -		if (results->enable_fbc_wm)
> +		if (!IS_GEN9(dev) && results->enable_fbc_wm)

This hunk is still bogus.

>  			val &= ~DISP_FBC_WM_DIS;
>  		else
>  			val |= DISP_FBC_WM_DIS;
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 18/24] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

[Ville Syrjälä]

On Fri, May 27, 2016 at 05:26:58PM +0300, Mika Kuoppala wrote:
> We need this gafs bit to be enabled for hw fix to
> take effect.
> 
> References: HSD#2227156, HSD#2227050
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77f5edc5f915..509238561935 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6084,6 +6084,7 @@ enum skl_disp_power_wells {
>  
>  #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
>  #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
> +#define GEN8_CS_CHICKEN2		_MMIO(0x2194)
>  
>  /* GEN7 chicken */
>  #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a1488712628b..b7b36c1cfdc3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1117,6 +1117,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
>  			GEN7_HALF_SLICE_CHICKEN1,
>  			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>  
> +	/* WaDisableGafsUnitClkGating:skl */
> +	WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));

Name the bit?

> +
>  	/* WaDisableLSQCROPERFforOCL:skl */
>  	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
>  	if (ret)
> @@ -1218,6 +1221,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
>  		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>  				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>  
> +	/* WaDisableGafsUnitClkGating:kbl */
> +	WA_SET_BIT(GEN8_CS_CHICKEN2, (1 << 1));
> +
>  	/* WaDisableLSQCROPERFforOCL:kbl */
>  	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
>  	if (ret)
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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✗ Ro.CI.BAT: failure for kbl and gen9 workarounds (rev6)

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds (rev6)
URL   : https://patchwork.freedesktop.org/series/7824/
State : failure

== Summary ==

Series 7824v6 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/6/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                pass       -> FAIL       (ro-byt-n2820)

fi-bdw-i7-5557u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-bsw-n3050     total:209  pass:167  dwarn:0   dfail:0   fail:2   skip:40 
fi-byt-n2820     total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-i7-4770r  total:209  pass:185  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
ro-bdw-i7-5557U failed to connect after reboot
ro-bdw-i7-5600u failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1039/

5c0712f drm-intel-nightly: 2016y-05m-27d-12h-32m-45s UTC integration manifest
bc80614 drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
766c92c drm/i195/fbc: Add WaFbcNukeOnHostModify
c6ca38e drm/i915/gen9: Add WaFbcWakeMemOn
a32f809 drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
a7bb5eb drm/i915/gen9: Add WaEnableChickenDCPR
32e6576 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
6e619c7 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
0a26681 drm/i915/kbl: Add WaForGAMHang
ca65e73 drm/i915/skl: Add WAC6entrylatency
5a8d1b2 drm/i915/gen9: Add WaDisableSkipCaching
e0537fa drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
0d5c560 drm/i915/kbl: Add WaDisableDynamicCreditSharing
c206682 drm/i915/kbl: Add WaDisableGamClockGating
29df3ca drm/i915/gen9: Enable must set chicken bits in config0 reg
37e3a6ae drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
b56d1a0 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
62e87ad drm/i915/kbl: Add WaDisableSDEUnitClockGating
736b4e2 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
7152d1fd drm/i915/kbl: Add WaEnableGapsTsvCreditFix
94f1b17 drm/i915: Mimic skl with WaForceEnableNonCoherent
77ebaac drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
00c5137 drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
54085f7 drm/i915/kbl: Add REVID macro
c70bd3c drm/i915/kbl: Init gen9 workarounds

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Re: [PATCH 07/24] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

[Chris Wilson]

On Fri, May 27, 2016 at 05:26:47PM +0300, Mika Kuoppala wrote:
> Add this workaround for kbl revid A0 only.

2 w/a in one patch, WaClearSlmSpaceAtContextSwitch:kbl is not mentioned
here.
-Chris

-- 
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[PATCH 07/25] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

[Mika Kuoppala]

Add this workaround for kbl revid A0 only.

v2: rebase
v3: carve out a non related workaround (Chris)

References: HSD#1911714
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c4232009b4a2..3963aeea90b1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1191,6 +1191,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 				   GEN9_GAPS_TSV_CREDIT_DISABLE));
 
+	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FENCE_DEST_SLM_DISABLE);
+
 	return 0;
 }
 
-- 
2.5.0

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[PATCH 18/25] drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl

[Mika Kuoppala]

We need this gafs bit to be enabled for hw fix to
take effect. The spec doesn't give name to this bit so
name it by assuming it's function.

v2: name the bit (Ville)

References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77f5edc5f915..313bb4b19d3d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6084,6 +6084,8 @@ enum skl_disp_power_wells {
 
 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
+#define GEN8_CS_CHICKEN2		_MMIO(0x2194)
+# define GEN8_CS_GAFS_DISABLE_CLK_GATING (1 << 1)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a1488712628b..92404427c7f4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1117,6 +1117,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
 			GEN7_HALF_SLICE_CHICKEN1,
 			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaDisableGafsUnitClkGating:skl */
+	WA_SET_BIT(GEN8_CS_CHICKEN2, GEN8_CS_GAFS_DISABLE_CLK_GATING);
+
 	/* WaDisableLSQCROPERFforOCL:skl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
@@ -1218,6 +1221,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
+	/* WaDisableGafsUnitClkGating:kbl */
+	WA_SET_BIT(GEN8_CS_CHICKEN2, GEN8_CS_GAFS_DISABLE_CLK_GATING);
+
 	/* WaDisableLSQCROPERFforOCL:kbl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 	if (ret)
-- 
2.5.0

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[PATCH 21/25] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

[Mika Kuoppala]

According to bspec this prevents screen corruption when fbc is
used.

v2: This workaround has a name, use it (Ville)
v3: remove bogus gen check on ilk/vlv wm path (Ville)

References: HSD#2135555, HSD#2137270, BSID#562
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ae1b0646678..6b972ae53bec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -68,6 +68,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaEnableChickenDCPR:skl,bxt,kbl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
+	I915_WRITE(DISP_ARB_CTL,
+		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
 }
 
 static void bxt_init_clock_gating(struct drm_device *dev)
-- 
2.5.0

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[PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

[Mika Kuoppala]

This workaround for bdw and chv, is also needed for kbl A0.

References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5b0f271b9d91..0612b6c8ffcf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1261,6 +1261,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 		return ret;
 	index = ret;
 
+	/* WaClearSlmSpaceAtContextSwitch:kbl */
+	/* Actual scratch location is at 128 bytes offset */
+	if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+		uint32_t scratch_addr
+			= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
+
+		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
+		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
+					   PIPE_CONTROL_GLOBAL_GTT_IVB |
+					   PIPE_CONTROL_CS_STALL |
+					   PIPE_CONTROL_QW_WRITE));
+		wa_ctx_emit(batch, index, scratch_addr);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+	}
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
 		wa_ctx_emit(batch, index, MI_NOOP);
-- 
2.5.0

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✗ Ro.CI.BAT: warning for kbl and gen9 workarounds (rev9)

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds (rev9)
URL   : https://patchwork.freedesktop.org/series/7824/
State : warning

== Summary ==

Series 7824v9 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/9/mbox

Test core_auth:
        Subgroup basic-auth:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_close_race:
        Subgroup basic-process:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_exec_basic:
        Subgroup gtt-render:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
        Subgroup basic-uc-set-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-small-copy:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-bsd:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-framebuffer-vs-set-tiling:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup addfb25-x-tiled-mismatch:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup addfb25-y-tiled-small:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-1024:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-63:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-x-tiled:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup framebuffer-vs-set-tiling:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup too-high:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup too-wide:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050     total:209  pass:167  dwarn:1   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:170  dwarn:0   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl-i7-6700hq total:204  pass:174  dwarn:9   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1054/

031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
a4ecb93 drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
17058c3 drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
bc62f73 drm/i195/fbc: Add WaFbcNukeOnHostModify
c3f9f60c drm/i915/gen9: Add WaFbcWakeMemOn
b707f34 drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
325b012 drm/i915/gen9: Add WaEnableChickenDCPR
80c3d70 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
68f9267 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
506b962 drm/i915/kbl: Add WaForGAMHang
3d2ca34 drm/i915/skl: Add WAC6entrylatency
58ef9a5 drm/i915/gen9: Add WaDisableSkipCaching
3505495 drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
ac86990 drm/i915/kbl: Add WaDisableDynamicCreditSharing
293add5 drm/i915/kbl: Add WaDisableGamClockGating
eaa7acc drm/i915/gen9: Enable must set chicken bits in config0 reg
7364db5 drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
df5f7f1 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
cc82ba6 drm/i915/kbl: Add WaDisableSDEUnitClockGating
3a14034 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
06ee86a drm/i915/kbl: Add WaEnableGapsTsvCreditFix
0efd467 drm/i915: Mimic skl with WaForceEnableNonCoherent
9e92264 drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
192a829 drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
d7e28fe drm/i915/kbl: Add REVID macro
f4bc1b5 drm/i915/kbl: Init gen9 workarounds

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Re: [PATCH 21/25] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark

[Ville Syrjälä]

On Mon, May 30, 2016 at 06:10:20PM +0300, Mika Kuoppala wrote:
> According to bspec this prevents screen corruption when fbc is
> used.
> 
> v2: This workaround has a name, use it (Ville)
> v3: remove bogus gen check on ilk/vlv wm path (Ville)
> 
> References: HSD#2135555, HSD#2137270, BSID#562
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9ae1b0646678..6b972ae53bec 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -68,6 +68,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  	/* WaEnableChickenDCPR:skl,bxt,kbl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> +
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> +	I915_WRITE(DISP_ARB_CTL,
> +		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
>  }
>  
>  static void bxt_init_clock_gating(struct drm_device *dev)
> -- 
> 2.5.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 02/24] drm/i915/kbl: Add REVID macro

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 03/24] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 04/24] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 23/24] drm/i195/fbc: Add WaFbcNukeOnHostModify

[Ville Syrjälä]

On Fri, May 27, 2016 at 05:27:03PM +0300, Mika Kuoppala wrote:
> Bspec states that we need to set nuke on modify all to prevent
> screen corruption with fbc on skl and kbl.
> 
> v2: proper workaround name
> 
> References: HSD#2227109, HSDES#1404569388
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2f3a3960f5f7..e08f29685b25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
>  #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
>  #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
>  #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> +#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1<<23)
>  #define ILK_FBC_RT_BASE		_MMIO(0x2128)
>  #define   ILK_FBC_RT_VALID	(1<<0)
>  #define   SNB_FBC_FRONT_BUFFER	(1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6d9cf487ea40..d4cbae4f3ce7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6887,6 +6887,10 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
>  	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
>  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaFbcNukeOnHostModify:kbl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
>  static void skylake_init_clock_gating(struct drm_device *dev)
> @@ -6898,6 +6902,10 @@ static void skylake_init_clock_gating(struct drm_device *dev)
>  	/* WAC6entrylatency:skl */
>  	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
>  		   FBC_LLC_FULLY_OPEN);
> +
> +	/* WaFbcNukeOnHostModify:skl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
>  static void broadwell_init_clock_gating(struct drm_device *dev)
> -- 
> 2.5.0
> 
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-- 
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Re: [PATCH 22/24] drm/i915/gen9: Add WaFbcWakeMemOn

[Ville Syrjälä]

On Fri, May 27, 2016 at 05:27:02PM +0300, Mika Kuoppala wrote:
> Set bit 8 in 0x43224 to prevent screen corruption and system
> hangs on high memory bandwidth conditions. The same wa also suggest
> setting bit 31 on ARB_CTL. According to another workaround we gain
> better idle power savings when FBC is enabled.
> 
> v2: use correct workaround name
> 
> References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 280d2137f90f..2f3a3960f5f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2208,6 +2208,7 @@ enum skl_disp_power_wells {
>  #define ILK_DPFC_STATUS		_MMIO(0x43210)
>  #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
>  #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
> +#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
>  #define ILK_FBC_RT_BASE		_MMIO(0x2128)
>  #define   ILK_FBC_RT_VALID	(1<<0)
>  #define   SNB_FBC_FRONT_BUFFER	(1<<1)
> @@ -6053,6 +6054,7 @@ enum skl_disp_power_wells {
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>  
>  #define DISP_ARB_CTL	_MMIO(0x45000)
> +#define  DISP_FBC_MEMORY_WAKE		(1<<31)
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  #define DISP_ARB_CTL2	_MMIO(0x45004)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b2acb82b302b..6d9cf487ea40 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -70,8 +70,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
>  	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	I915_WRITE(DISP_ARB_CTL,
> -		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
> +	/* WaFbcWakeMemOn:skl,bxt,kbl */
> +	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> +		   DISP_FBC_WM_DIS |
> +		   DISP_FBC_MEMORY_WAKE);
> +
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_DISABLE_DUMMY0);

I think we might have two partially overlapping w/as here:
WaFbcWakeMemOn and WaFbcHighMemBwCorruptionAvoidance. Not sure if the
latter applies to all of KBL. w/a db says all, bspec says a0,b0 only.

Might want to add the other w/a name as well at least. With that this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
>  static void bxt_init_clock_gating(struct drm_device *dev)
> -- 
> 2.5.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 05/24] drm/i915: Mimic skl with WaForceEnableNonCoherent

[Matthew Auld]

s/tho/though/
s/regarless/regardless/

Seems reasonable so:

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Re: [PATCH 06/24] drm/i915/kbl: Add WaEnableGapsTsvCreditFix

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 01/24] drm/i915/kbl: Init gen9 workarounds

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 07/25] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 08/24] drm/i915/kbl: Add WaDisableSDEUnitClockGating

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 09/24] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 10/24] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

[Matthew Auld]

>  #define KBL_REVID_A0           0x0
>  #define KBL_REVID_B0           0x1
> +#define KBL_REVID_C0           0x2
> +#define KBL_REVID_D0           0x3
> +#define KBL_REVID_E0           0x3

hmm, shouldn't E0 here be 0x4?
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[PATCH 10/25] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

[Mika Kuoppala]

Extend the scope of this workaround, already used in skl,
to also take effect in kbl.

v2: Fix KBL_REVID_E0 (Matthew)

References: HSD#2132677
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c        |  5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eaa21ac3512e..b680fdb65ccd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2719,6 +2719,9 @@ struct drm_i915_cmd_table {
 
 #define KBL_REVID_A0		0x0
 #define KBL_REVID_B0		0x1
+#define KBL_REVID_C0		0x2
+#define KBL_REVID_D0		0x3
+#define KBL_REVID_E0		0x4
 
 #define IS_KBL_REVID(p, since, until) \
 	(IS_KABYLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1afaaf..e807b564bfab 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1081,12 +1081,13 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
 	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
 
 	/*
-	 * WaDisableLSQCROPERFforOCL:skl
+	 * WaDisableLSQCROPERFforOCL:skl,kbl
 	 * This WA is implemented in skl_init_clock_gating() but since
 	 * this batch updates GEN8_L3SQCREG4 with default value we need to
 	 * set this bit here to retain the WA during flush.
 	 */
-	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
+	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0) ||
+	    IS_KBL_REVID(engine->i915, 0, KBL_REVID_E0))
 		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
 
 	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3963aeea90b1..dd743d988b1a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1196,6 +1196,19 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
 				  HDC_FENCE_DEST_SLM_DISABLE);
 
+	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+	 * involving this register should also be added to WA batch as required.
+	 */
+	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+		/* WaDisableLSQCROPERFforOCL:kbl */
+		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			   GEN8_LQSC_RO_PERF_DIS);
+
+	/* WaDisableLSQCROPERFforOCL:kbl */
+	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
2.7.4

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Re: [PATCH 11/24] drm/i915/gen9: Enable must set chicken bits in config0 reg

[Matthew Auld]

> +#define  GEN9_DEFAULT_FIXES            (1<<3 | 1<<2 | 1 << 1)
Spacing seems a little off here

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Re: [PATCH 14/24] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 16/24] drm/i915/skl: Add WAC6entrylatency

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 19/24] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 24/24] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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✗ Ro.CI.BAT: warning for kbl and gen9 workarounds (rev10)

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds (rev10)
URL   : https://patchwork.freedesktop.org/series/7824/
State : warning

== Summary ==

Series 7824v10 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/10/mbox

Test core_auth:
        Subgroup basic-auth:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_cs_tlb:
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-uc-pro-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-uc-prw-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-uc-ro-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-wb-rw-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-copy:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-small-copy:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-small-copy-xy:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-write-cpu-read-gtt:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-write-gtt:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-write-no-prefault:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup bad-pitch-1024:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-256:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_frontbuffer_tracking:
        Subgroup basic:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050     total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:82   pass:64   dwarn:0   dfail:0   fail:0   skip:17 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl-i7-6700hq total:204  pass:179  dwarn:4   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1081/

4e3459b drm-intel-nightly: 2016y-06m-02d-13h-13m-15s UTC integration manifest
7e89439 drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
0aa2541 drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
7546564 drm/i195/fbc: Add WaFbcNukeOnHostModify
0b2bb0b drm/i915/gen9: Add WaFbcWakeMemOn
c2f3d1a drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
3f274e4 drm/i915/gen9: Add WaEnableChickenDCPR
1afd252 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
80f10d3 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
d56bd66 drm/i915/kbl: Add WaForGAMHang
08e79fb drm/i915/skl: Add WAC6entrylatency
6d9fe0b drm/i915/gen9: Add WaDisableSkipCaching
c366d38 drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
06fe4e4 drm/i915/kbl: Add WaDisableDynamicCreditSharing
91f49b1 drm/i915/kbl: Add WaDisableGamClockGating
5212c7d drm/i915/gen9: Enable must set chicken bits in config0 reg
2857496 drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
c584a14 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
7b07109 drm/i915/kbl: Add WaDisableSDEUnitClockGating
31a2da0 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
49a8ed3 drm/i915/kbl: Add WaEnableGapsTsvCreditFix
84b17d8 drm/i915: Mimic skl with WaForceEnableNonCoherent
cf79504 drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
6757b15 drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
dbf3c22 drm/i915/kbl: Add REVID macro
55d9b47 drm/i915/kbl: Init gen9 workarounds

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Re: [PATCH 12/24] drm/i915/kbl: Add WaDisableGamClockGating

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 17/24] drm/i915/kbl: Add WaForGAMHang

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 20/24] drm/i915/gen9: Add WaEnableChickenDCPR

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

[Matthew Auld]

What about skl, this also seems to need the WA until A0?
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Re: [PATCH 13/24] drm/i915/kbl: Add WaDisableDynamicCreditSharing

[Matthew Auld]

> +       /* WaDisableDynamicCreditSharing:kbl */
> +       if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
> +               WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28));
> +
Let's play name that bit!

Otherwise the patch looks good, although slightly worrying that the
hsd's state the WA is needed up to B0, but the WA db says up to A0...

I guess we should rather trust the hsd's?

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

[Arun Siluvery]

On 03/06/2016 21:31, Matthew Auld wrote:
> What about skl, this also seems to need the WA until A0?

SKL:A0 is pre-production stepping, it can be ignored.

regards
Arun

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Re: [PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

[Matthew Auld]

On 4 June 2016 at 09:54, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
> On 03/06/2016 21:31, Matthew Auld wrote:
>>
>> What about skl, this also seems to need the WA until A0?
>
>
> SKL:A0 is pre-production stepping, it can be ignored.
>
> regards
> Arun
>
>
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>

In which case this patch is:

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 13/24] drm/i915/kbl: Add WaDisableDynamicCreditSharing

[Mika Kuoppala]

Matthew Auld <matthew.william.auld@gmail.com> writes:

> [ text/plain ]
>> +       /* WaDisableDynamicCreditSharing:kbl */
>> +       if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
>> +               WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28));
>> +
> Let's play name that bit!
>
> Otherwise the patch looks good, although slightly worrying that the
> hsd's state the WA is needed up to B0, but the WA db says up to A0...
>
> I guess we should rather trust the hsd's?

Yes I consider hsd's the authoritative source.

-Mika



>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

[Mika Kuoppala]

Arun Siluvery <arun.siluvery@linux.intel.com> writes:

> [ text/plain ]
> On 03/06/2016 21:31, Matthew Auld wrote:
>> What about skl, this also seems to need the WA until A0?
>
> SKL:A0 is pre-production stepping, it can be ignored.
>

Yes, the rationale here was that we have kbl:A0 around still
but there are no skl:A0 in use that we care.

-Mika


> regards
> Arun
>
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Re: [PATCH 22/24] drm/i915/gen9: Add WaFbcWakeMemOn

[Mika Kuoppala]

Ville Syrjälä <ville.syrjala@linux.intel.com> writes:

> [ text/plain ]
> On Fri, May 27, 2016 at 05:27:02PM +0300, Mika Kuoppala wrote:
>> Set bit 8 in 0x43224 to prevent screen corruption and system
>> hangs on high memory bandwidth conditions. The same wa also suggest
>> setting bit 31 on ARB_CTL. According to another workaround we gain
>> better idle power savings when FBC is enabled.
>> 
>> v2: use correct workaround name
>> 
>> References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 2 ++
>>  drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
>>  2 files changed, 9 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 280d2137f90f..2f3a3960f5f7 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2208,6 +2208,7 @@ enum skl_disp_power_wells {
>>  #define ILK_DPFC_STATUS		_MMIO(0x43210)
>>  #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
>>  #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
>> +#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
>>  #define ILK_FBC_RT_BASE		_MMIO(0x2128)
>>  #define   ILK_FBC_RT_VALID	(1<<0)
>>  #define   SNB_FBC_FRONT_BUFFER	(1<<1)
>> @@ -6053,6 +6054,7 @@ enum skl_disp_power_wells {
>>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>>  
>>  #define DISP_ARB_CTL	_MMIO(0x45000)
>> +#define  DISP_FBC_MEMORY_WAKE		(1<<31)
>>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>>  #define  DISP_FBC_WM_DIS		(1<<15)
>>  #define DISP_ARB_CTL2	_MMIO(0x45004)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index b2acb82b302b..6d9cf487ea40 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -70,8 +70,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>>  
>>  	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
>> -	I915_WRITE(DISP_ARB_CTL,
>> -		   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
>> +	/* WaFbcWakeMemOn:skl,bxt,kbl */
>> +	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> +		   DISP_FBC_WM_DIS |
>> +		   DISP_FBC_MEMORY_WAKE);
>> +
>> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +		   ILK_DPFC_DISABLE_DUMMY0);
>
> I think we might have two partially overlapping w/as here:
> WaFbcWakeMemOn and WaFbcHighMemBwCorruptionAvoidance. Not sure if the
> latter applies to all of KBL. w/a db says all, bspec says a0,b0 only.
>
> Might want to add the other w/a name as well at least. With that this is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>

I decided to split this for WaFbcNukeOnHostModify
and WaFbcHighMemBwCorruptionAvoidance.

-Mika



>>  }
>>  
>>  static void bxt_init_clock_gating(struct drm_device *dev)
>> -- 
>> 2.5.0
>> 
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>
> -- 
> Ville Syrjälä
> Intel OTC
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Re: [PATCH 10/25] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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Re: [PATCH 15/24] drm/i915/gen9: Add WaDisableSkipCaching

[Matthew Auld]

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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