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Tue, 06 Dec 2022 08:58:35 -0800 (PST) MIME-Version: 1.0 References: <97b42ba0ae91b1ed6feb6e5c090bff2445719bf7.1670311877.git.aravind.iddamsetty@intel.com> In-Reply-To: From: Matthew Auld Date: Tue, 6 Dec 2022 16:58:07 +0000 Message-ID: To: Aravind Iddamsetty Content-Type: text/plain; charset="UTF-8" Subject: Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl/UAPI: Disable GET/SET_CACHING IOCTL for MTL+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pallavi Mishra , intel-gfx@lists.freedesktop.org, Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 6 Dec 2022 at 08:13, Aravind Iddamsetty wrote: > > From: Pallavi Mishra > > It's a noop on all new platforms starting from MTL. > Refer: (e7737b67ab46) drm/i915/uapi: reject caching ioctls for discrete > > v2: > 1. block get caching ioctl > 2. return ENODEV similar to DGFX > 3. update the doc in i915_drm.h > > Cc: Lucas De Marchi > Cc: Matt Roper > Cc: Joonas Lahtinen > > Signed-off-by: Pallavi Mishra > Signed-off-by: Aravind Iddamsetty > --- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 4 ++-- > include/uapi/drm/i915_drm.h | 3 +++ > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index d44a152ce680..cf817ee0aa01 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -291,7 +291,7 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, > struct drm_i915_gem_object *obj; > int err = 0; > > - if (IS_DGFX(to_i915(dev))) > + if (IS_DGFX(to_i915(dev)) || GRAPHICS_VER_FULL(to_i915(dev)) >= IP_VER(12, 70)) > return -ENODEV; > > rcu_read_lock(); > @@ -329,7 +329,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, > enum i915_cache_level level; > int ret = 0; > > - if (IS_DGFX(i915)) > + if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > return -ENODEV; > > switch (args->caching) { > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 8df261c5ab9b..3467fd879427 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -1626,6 +1626,9 @@ struct drm_i915_gem_busy { > * - Everything else is always allocated and mapped as write-back, with the > * guarantee that everything is also coherent with the GPU. > * > + * Starting from MTL even on integrated platforms set/get caching is no longer > + * supported and object will be mapped as write-combined only. Just a drive-by-comment. I assume you meant uncached here, right? i.e CACHE_NONE. > + * > * Note that this is likely to change in the future again, where we might need > * more flexibility on future devices, so making this all explicit as part of a > * new &drm_i915_gem_create_ext extension is probable. > -- > 2.25.1 >