From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mail.openembedded.org (Postfix) with ESMTP id 341A17D25F for ; Thu, 7 Nov 2019 00:55:16 +0000 (UTC) Received: by mail-qk1-f180.google.com with SMTP id i19so520023qki.2 for ; Wed, 06 Nov 2019 16:55:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nLTTG16+wXyXy2oaxjGA0M6Dotxz7YkDDMAbCSHhpFI=; b=WUq5YPhSiqyT75shjtJIMKKc5vCkJMHSe7wANHClc7/TbVHA+7CXuYgB+7CAwEUksw vCOJQicmp9oOO/BpA158IweuFWkuWt8iGNvIPhK7wkgTEssAgiDIRhJHxEwhKRCtqJQ7 sQeH9AQCRH0KS3+OItXQUForjo3OmqvxaDfJ00wEUTcp19y7vCrfTWfIY3sz3d4suphK THKKlrf9qTtPAo56JmBRLCvmpxGyDKXJxTo6uDvH5tOM7uIk8ABVcM1ZPqFOCKpr6kIy UDND1vp1Jcsd+OQrqstM8lietutzU/Bo+I6f34e1sq+k2XfzW2+R+u3wXY465WmS1C46 fQcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nLTTG16+wXyXy2oaxjGA0M6Dotxz7YkDDMAbCSHhpFI=; b=opm7LhLZVAUF5LiFiaAlHw6TGkr1NPD9YnCP7iBLD7EfrCTV4a+o3ZFoR6zdLAPyOr NjuOb/vw/+AVnlMZTiBtlGa18RtMS/C5CHV02fslyJTOfxvKjzHkydyPlWHn5CjSL2Wg XZVe8gWMvwW3gvKuOJdH50+zjbWpvnpVUZLvRWx+jtARa7DZXFoVQ4o109OOtlHnRXtd 9+b0pDtfih5XGHlBwueZgYD7g/54scaNZ5sjHdkW2s7Gao4eqNDSh5qhNEXI7HeQzOBv 4e9o4NJUuyttEOszddiEqB+Hma8Htua6R45cWTffWPWLdtXj0jPjDXteHRp4ZBCKhfIy 4zug== X-Gm-Message-State: APjAAAUAJXTqqAGxjaNe03tTMhkH5KfhT/x62HZCCG7a8xchwS1YiQor FsduI6hrqihWkudemGwFihHu/20jm4YnIv/9qE2+dqYZ X-Google-Smtp-Source: APXvYqyR/5bnerx2P6ww4+Jvi7iOYcJVCXa4cgUceudtuBbwGMNcnfZDiJzsZlPQKwIZchaRl7zNqWuZQdhrx5IwZhY= X-Received: by 2002:a37:4bc2:: with SMTP id y185mr283256qka.474.1573088116571; Wed, 06 Nov 2019 16:55:16 -0800 (PST) MIME-Version: 1.0 References: <20191106181819.12517-1-alistair.francis@wdc.com> <20191106221250.GD14721@localhost> In-Reply-To: From: Khem Raj Date: Wed, 6 Nov 2019 16:55:05 -0800 Message-ID: To: Alistair Francis Cc: "openembedded-core@lists.openembedded.org" , "bunk@stusta.de" Subject: Re: [PATCH 1/2] tune-riscv: Add support for hard and soft float X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Nov 2019 00:55:16 -0000 Content-Type: multipart/alternative; boundary="0000000000006382de0596b71e1d" --0000000000006382de0596b71e1d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Nov 6, 2019 at 4:48 PM Alistair Francis wrote: > On Thu, 2019-11-07 at 00:12 +0200, Adrian Bunk wrote: > > On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote: > > > ... > > > +TUNE_CCARGS_riscv64 .=3D "${@bb.utils.contains('TUNE_FEATURES', > > > 'riscv64-f', ' -mabi=3Dlp64d', ' -mabi=3Dlp64', d)}" > > > +TUNE_CCARGS_riscv32 .=3D "${@bb.utils.contains('TUNE_FEATURES', > > > 'riscv32-f', ' -mabi=3Dilp32f', ' -mabi=3Dilp32', d)}" > > > ... > > > > That looks wrong, what would you put in TUNE_FEATURES > > for -mabi=3Dlp64f when -mabi=3Dlp64d is called riscv64-f? > > I am just going to add riscv32nf and riscv64nf. This will specify > -mabi=3Dilp32 and -mabi=3Dlp64 accordingly. I won't change the default > riscv32 and riscv64. We can then deal with the single and double float > at a later point. > > > > > Also note that this is only the floating point calling convention, > > whether the compiler emits floating point instructions is defined > > by -march. > > -march is another can of worms that I was trying to avoid. I don't have > a good way of handling the ISA strings at the moment without some crazy > number of tune options. We need to handle that but I think that should be in meta-riscv since I think for Linux we should just stick to rv64gc ABI and something cross distro agreed upon abi for riscv32 and bare metal is another story that=E2= =80=99s where probably we need to address the ABIs > > > > > > It would be good if this would start with a plan how to handle > > all possible combination of RISC-V ISA extensions, ideally better > > than the arm mess. > > Agreed. I am just going to change this to add a no float option as that > fixes a large number of 32-bit link failures (seen in U-Boot, OpenSBI > and SDKs) and we can re-evaluate a longer term march fix. This is fine to start with for now > > Alistair > > > > > cu > > Adrian > > > -- > _______________________________________________ > Openembedded-core mailing list > Openembedded-core@lists.openembedded.org > http://lists.openembedded.org/mailman/listinfo/openembedded-core > --0000000000006382de0596b71e1d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Wed, Nov 6, 2019 at 4:48 PM Alistair Francis <Alistair.Francis@wdc.com> wrote= :
On Thu, 2019-11-07 at 00:12 +0200= , Adrian Bunk wrote:
> On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> > ...
> > +TUNE_CCARGS_riscv64 .=3D "${@bb.utils.contains('TUNE_FE= ATURES',
> > 'riscv64-f', ' -mabi=3Dlp64d', ' -mabi=3Dlp64= ', d)}"
> > +TUNE_CCARGS_riscv32 .=3D "${@bb.utils.contains('TUNE_FE= ATURES',
> > 'riscv32-f', ' -mabi=3Dilp32f', ' -mabi=3Dilp= 32', d)}"
> > ...
>
> That looks wrong, what would you put in TUNE_FEATURES
> for -mabi=3Dlp64f when -mabi=3Dlp64d is called riscv64-f?

I am just going to add riscv32nf and riscv64nf. This will specify
-mabi=3Dilp32 and -mabi=3Dlp64 accordingly. I won't change the default<= br> riscv32 and riscv64. We can then deal with the single and double float
at a later point.

>
> Also note that this is only the floating point calling convention,
> whether the compiler emits floating point instructions is defined
> by -march.

-march is another can of worms that I was trying to avoid. I don't have=
a good way of handling the ISA strings at the moment without some crazy
number of tune options.

We need to handle that but I think that should be in meta-riscv sinc= e I think for Linux we should just stick to rv64gc ABI and something cross = distro agreed upon abi for riscv32 and bare metal is another story that=E2= =80=99s where probably we need to address the ABIs=C2=A0


>
> It would be good if this would start with a plan how to handle
> all possible combination of RISC-V ISA extensions, ideally better
> than the arm mess.

Agreed. I am just going to change this to add a no float option as that
fixes a large number of 32-bit link failures (seen in U-Boot, OpenSBI
and SDKs) and we can re-evaluate a longer term march fix.

This is fine to start with for now=



Alistair

>
> cu
> Adrian
>
--
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