From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eitan Kaplan Subject: Registering interrupt handler for performance counter overflow Date: Sun, 19 May 2019 14:46:30 -0400 Message-ID: Reply-To: e.kaplan@columbia.edu Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============4514441424258129037==" Return-path: Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hSQpb-0005wC-1B for xen-devel@lists.xenproject.org; Sun, 19 May 2019 18:46:47 +0000 Received: from hazelnut (hazelnut.cc.columbia.edu [128.59.213.250]) by outprodmail01.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id x4JIh5Ii007948 for ; Sun, 19 May 2019 14:46:42 -0400 Received: from hazelnut (localhost.localdomain [127.0.0.1]) by hazelnut (Postfix) with ESMTP id BD0D56D for ; Sun, 19 May 2019 14:46:42 -0400 (EDT) Received: from sendprodmail01.cc.columbia.edu (sendprodmail01.cc.columbia.edu [128.59.72.13]) by hazelnut (Postfix) with ESMTP id 9EE616D for ; Sun, 19 May 2019 14:46:42 -0400 (EDT) Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by sendprodmail01.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id x4JIkg2w033272 (version=TLSv1/SSLv3 cipher=AES128-GCM-SHA256 bits=128 verify=NOT) for ; Sun, 19 May 2019 14:46:42 -0400 Received: by mail-qt1-f200.google.com with SMTP id n21so12165477qtp.15 for ; Sun, 19 May 2019 11:46:42 -0700 (PDT) List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: xen-devel@lists.xenproject.org List-Id: xen-devel@lists.xenproject.org --===============4514441424258129037== Content-Type: multipart/alternative; boundary="0000000000005b5878058942093f" --0000000000005b5878058942093f Content-Type: text/plain; charset="UTF-8" Hi all, I am a computer engineering student at Columbia University. This is my first time writing to this list (please let me know if this isn't the place for this type of question!). I am working with a professor on a project to mitigate Spectre and Meltdown (and other similar cache timing side-channel attacks). We are using Xen and modifying its source as a way of modeling the affect certain potential hardware changes. As part of that project, we need to use the performance counters to generate interrupts at certain microarchitectural events. I have successfully added into xen/arch/x86/setup.c a few lines to setup the (Intel Sandy Bridge) performance counter control MSRs and set the counter itself to a few below overflow. All that's missing is a simple interrupt handler that will reset the counter to a few below overflow (and perhaps do some logging). I am having trouble figuring out how to register my handler in Xen. I assume that I have to call request_irq(), but I am not sure how to set all the arguments for that call. Would anyone be able to give me any pointers? Suggestions or pointers to resources/examples for registering interrupt handlers in Xen would be really helpful! Alternatively, is there an existing interrupt handler that is already setup for PMC overflow interrupts that I might be able to tweak? Thank you! Eitan Kaplan --0000000000005b5878058942093f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi all,

I am a computer engineering stu= dent at Columbia University. This is my first time writing to this list (pl= ease let me know if this isn't the place for this type of question!).

I am working with a professor on a project to mitig= ate Spectre and Meltdown (and other similar cache timing side-channel attac= ks).=C2=A0 We are using Xen and modifying its source as a way of modeling t= he affect certain potential hardware changes. As part of that project, we n= eed to use the performance counters to generate interrupts at certain micro= architectural events.=C2=A0 I have successfully added into xen/arch/x86/set= up.c a few lines to setup the (Intel Sandy Bridge) performance counter cont= rol MSRs and set the counter itself to a few below overflow.=C2=A0 All that= 's missing is a simple interrupt handler that will reset the counter to= a few below overflow (and perhaps do some logging).

I am having trouble figuring out how to register my handler in Xen.=C2= =A0 I assume that I have to call request_irq(), but I am not sure how to se= t all the arguments for that call.=C2=A0 Would anyone be able to give me an= y pointers?=C2=A0 Suggestions or pointers to resources/examples for registe= ring interrupt handlers in Xen would be really helpful!

Alternatively, is there an existing interrupt handler that is already= setup for PMC overflow interrupts that I might be able to tweak?

Thank you!
Eitan Kaplan
--0000000000005b5878058942093f-- --===============4514441424258129037== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0 cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== --===============4514441424258129037==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, HTML_MESSAGE,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23659C04AB4 for ; Sun, 19 May 2019 18:47:06 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2EAF20578 for ; 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Sun, 19 May 2019 11:46:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqz65PhXrhzapdLQntz2J0YAUCRsPTTnKeh95RvI7eBZOcHYGlvzjTZg1cMMnCpKdBmZwyP0X3nE7yeviDXHUDo= X-Received: by 2002:a05:620a:1085:: with SMTP id g5mr38953508qkk.182.1558291601376; Sun, 19 May 2019 11:46:41 -0700 (PDT) MIME-Version: 1.0 From: Eitan Kaplan Date: Sun, 19 May 2019 14:46:30 -0400 Message-ID: To: xen-devel@lists.xenproject.org X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.84 on 128.59.72.13 Subject: [Xen-devel] Registering interrupt handler for performance counter overflow X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Reply-To: e.kaplan@columbia.edu Content-Type: multipart/mixed; boundary="===============4514441424258129037==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Message-ID: <20190519184630.AMjXOiFVNCH3w4jKFqG2QoIQFMdYpneRiXkxKbF_O3Q@z> --===============4514441424258129037== Content-Type: multipart/alternative; boundary="0000000000005b5878058942093f" --0000000000005b5878058942093f Content-Type: text/plain; charset="UTF-8" Hi all, I am a computer engineering student at Columbia University. This is my first time writing to this list (please let me know if this isn't the place for this type of question!). I am working with a professor on a project to mitigate Spectre and Meltdown (and other similar cache timing side-channel attacks). We are using Xen and modifying its source as a way of modeling the affect certain potential hardware changes. As part of that project, we need to use the performance counters to generate interrupts at certain microarchitectural events. I have successfully added into xen/arch/x86/setup.c a few lines to setup the (Intel Sandy Bridge) performance counter control MSRs and set the counter itself to a few below overflow. All that's missing is a simple interrupt handler that will reset the counter to a few below overflow (and perhaps do some logging). I am having trouble figuring out how to register my handler in Xen. I assume that I have to call request_irq(), but I am not sure how to set all the arguments for that call. Would anyone be able to give me any pointers? Suggestions or pointers to resources/examples for registering interrupt handlers in Xen would be really helpful! Alternatively, is there an existing interrupt handler that is already setup for PMC overflow interrupts that I might be able to tweak? Thank you! Eitan Kaplan --0000000000005b5878058942093f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi all,

I am a computer engineering stu= dent at Columbia University. This is my first time writing to this list (pl= ease let me know if this isn't the place for this type of question!).

I am working with a professor on a project to mitig= ate Spectre and Meltdown (and other similar cache timing side-channel attac= ks).=C2=A0 We are using Xen and modifying its source as a way of modeling t= he affect certain potential hardware changes. As part of that project, we n= eed to use the performance counters to generate interrupts at certain micro= architectural events.=C2=A0 I have successfully added into xen/arch/x86/set= up.c a few lines to setup the (Intel Sandy Bridge) performance counter cont= rol MSRs and set the counter itself to a few below overflow.=C2=A0 All that= 's missing is a simple interrupt handler that will reset the counter to= a few below overflow (and perhaps do some logging).

I am having trouble figuring out how to register my handler in Xen.=C2= =A0 I assume that I have to call request_irq(), but I am not sure how to se= t all the arguments for that call.=C2=A0 Would anyone be able to give me an= y pointers?=C2=A0 Suggestions or pointers to resources/examples for registe= ring interrupt handlers in Xen would be really helpful!

Alternatively, is there an existing interrupt handler that is already= setup for PMC overflow interrupts that I might be able to tweak?

Thank you!
Eitan Kaplan
--0000000000005b5878058942093f-- --===============4514441424258129037== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0 cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== --===============4514441424258129037==--