From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 685A2C433EF for ; Mon, 28 Feb 2022 12:58:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbiB1M6p (ORCPT ); Mon, 28 Feb 2022 07:58:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232605AbiB1M6n (ORCPT ); Mon, 28 Feb 2022 07:58:43 -0500 Received: from mail-yb1-xb2d.google.com (mail-yb1-xb2d.google.com [IPv6:2607:f8b0:4864:20::b2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB098506D7; Mon, 28 Feb 2022 04:58:04 -0800 (PST) Received: by mail-yb1-xb2d.google.com with SMTP id h126so5396815ybc.1; Mon, 28 Feb 2022 04:58:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cPns1/npz7Dlc50rQYvlC2uiB8hqGLU7hoL0Zgx0XJ0=; b=pEolgqNiqpxngoF3DgV5antmR2xK1ESw6GfdlgaC1VRT62KrVi1FE94NVxvHe2y040 DCgDJOZ8s0kSQSPw6C9sx78FJavBTotCFHL/anc4DfXGcrgvPo8okv1JUkhqVfi/se9i hW06Ah3qyMKaaKOTNtTu8wbusrbB7phNlPF+AySvdDIO7u1QsCzFU7mpPGJHlzk9Mby6 UdsH3Nd6/98kA7DwkBYhjYGX9ZL6TzuOELKMCJfbDGjyY8VVL4mqSLXGaumytYsPQ2HJ 9J/sCwpo1GpeL79zD5T/i/qLvHLVrKyKmbC72hCBVyK1VCZmw12EYO+c52RVTUKHhVzh rDoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cPns1/npz7Dlc50rQYvlC2uiB8hqGLU7hoL0Zgx0XJ0=; b=UDc3wWgvAiDsxDBd8oRzclr4XX1NBcSMdez0RVuFiFiclm12iU4YDvY1t5MjuwAu2+ E/XEm1iGejBesR9VoKpGeDyeVH2nLy5k7OmGXqgVIecpjJBPQfOA2JBtirMqtI4zuj3r DL7UT/K8St9v1zJ8eAEur0z1Qwz8sXRmAZgR+jDRaY2rBIzBUd96Bu3TYcsma70StjVD f+aENmhB1Uq3VTVu97q/LtfrlG0vUgkNNb0g7ukPx0DFy8xYzQpZJS1OIZhiyfm2B3l8 NTfWUf9oDFoIqhx2JE22sbWQZkOxIZAbCH7jWAKcJnM2dGx6BKuTss89Pg2Hr04etmW9 XSJg== X-Gm-Message-State: AOAM533bzQ0COzHYLi4oKO4LKs3kcpv5HJgz27uM9SkHHmclO38ckiNq l7LknXgYZTfWJdbMlL4FQT+QswfiFsqt5tHOLQM= X-Google-Smtp-Source: ABdhPJyMMcn4V8F4Xi286fHhfGSOe0I5iwgQNzJBxzAM62I7vOIac08EqoIzl0comFG8kmVNvryVHX5S6ObASHPyNZo= X-Received: by 2002:a25:5145:0:b0:61d:ad99:6e5a with SMTP id f66-20020a255145000000b0061dad996e5amr18295765ybb.228.1646053084143; Mon, 28 Feb 2022 04:58:04 -0800 (PST) MIME-Version: 1.0 References: <20220227153016.950473-1-pgwipeout@gmail.com> <20220227153016.950473-6-pgwipeout@gmail.com> In-Reply-To: From: Peter Geis Date: Mon, 28 Feb 2022 07:57:52 -0500 Message-ID: Subject: Re: [PATCH v3 5/7] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes To: Michael Riesch Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , Johan Jonker , devicetree , arm-mail-list , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 28, 2022 at 2:24 AM Michael Riesch wrote: > > Hi Peter, > > On 2/27/22 16:30, Peter Geis wrote: > > Add the dwc3 device nodes to the rk356x device trees. > > The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > > > Signed-off-by: Peter Geis > > --- > > arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++ > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++ > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++- > > 3 files changed, 54 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > index 3839eef5e4f7..0b957068ff89 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > @@ -6,6 +6,10 @@ / { > > compatible = "rockchip,rk3566"; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3566-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>; > > + phy-names = "usb2-phy"; > > + extcon = <&usb2phy0>; > > I wonder what the correct place for this extcon property is. You defined > it on SoC (RK3566) level, in my patch for the RK3568 EVB1 it is added on > board level. Is this common to all RK356x variants? Yes, the usb2phy is always available as an extcon unless you make a device that doesn't have usb2 capability. In that case you'd have to override the device anyways. If we want to turn on default role otg here, we'd need this defined here as well or things break. > > Best regards, > Michael > > > + maximum-speed = "high-speed"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > index 5b0f528d6818..8ba9334f9753 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > @@ -99,6 +99,10 @@ opp-1992000000 { > > }; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > index 7cdef800cb3c..072bb9080cd6 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > @@ -230,6 +230,40 @@ scmi_shmem: sram@0 { > > }; > > }; > > > > + usb_host0_xhci: usb@fcc00000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfcc00000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, > > + <&cru ACLK_USB3OTG0>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG0>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > + usb_host1_xhci: usb@fd000000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfd000000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, > > + <&cru ACLK_USB3OTG1>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG1>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > gic: interrupt-controller@fd400000 { > > compatible = "arm,gic-v3"; > > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > > @@ -297,7 +331,6 @@ pmu_io_domains: io-domains { > > }; > > > > pipegrf: syscon@fdc50000 { > > - compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > reg = <0x0 0xfdc50000 0x0 0x1000>; > > }; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD912C433FE for ; Mon, 28 Feb 2022 13:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 28 Feb 2022 04:58:04 -0800 (PST) MIME-Version: 1.0 References: <20220227153016.950473-1-pgwipeout@gmail.com> <20220227153016.950473-6-pgwipeout@gmail.com> In-Reply-To: From: Peter Geis Date: Mon, 28 Feb 2022 07:57:52 -0500 Message-ID: Subject: Re: [PATCH v3 5/7] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes To: Michael Riesch Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , Johan Jonker , devicetree , arm-mail-list , Linux Kernel Mailing List X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220228_045805_512286_3E075F15 X-CRM114-Status: GOOD ( 22.26 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Mon, Feb 28, 2022 at 2:24 AM Michael Riesch wrote: > > Hi Peter, > > On 2/27/22 16:30, Peter Geis wrote: > > Add the dwc3 device nodes to the rk356x device trees. > > The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > > > Signed-off-by: Peter Geis > > --- > > arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++ > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++ > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++- > > 3 files changed, 54 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > index 3839eef5e4f7..0b957068ff89 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > @@ -6,6 +6,10 @@ / { > > compatible = "rockchip,rk3566"; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3566-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>; > > + phy-names = "usb2-phy"; > > + extcon = <&usb2phy0>; > > I wonder what the correct place for this extcon property is. You defined > it on SoC (RK3566) level, in my patch for the RK3568 EVB1 it is added on > board level. Is this common to all RK356x variants? Yes, the usb2phy is always available as an extcon unless you make a device that doesn't have usb2 capability. In that case you'd have to override the device anyways. If we want to turn on default role otg here, we'd need this defined here as well or things break. > > Best regards, > Michael > > > + maximum-speed = "high-speed"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > index 5b0f528d6818..8ba9334f9753 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > @@ -99,6 +99,10 @@ opp-1992000000 { > > }; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > index 7cdef800cb3c..072bb9080cd6 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > @@ -230,6 +230,40 @@ scmi_shmem: sram@0 { > > }; > > }; > > > > + usb_host0_xhci: usb@fcc00000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfcc00000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, > > + <&cru ACLK_USB3OTG0>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG0>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > + usb_host1_xhci: usb@fd000000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfd000000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, > > + <&cru ACLK_USB3OTG1>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG1>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > gic: interrupt-controller@fd400000 { > > compatible = "arm,gic-v3"; > > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > > @@ -297,7 +331,6 @@ pmu_io_domains: io-domains { > > }; > > > > pipegrf: syscon@fdc50000 { > > - compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > reg = <0x0 0xfdc50000 0x0 0x1000>; > > }; > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79A9AC433F5 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 28, 2022 at 2:24 AM Michael Riesch wrote: > > Hi Peter, > > On 2/27/22 16:30, Peter Geis wrote: > > Add the dwc3 device nodes to the rk356x device trees. > > The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable > > dwc3 host controller. > > > > Signed-off-by: Peter Geis > > --- > > arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++ > > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++ > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++- > > 3 files changed, 54 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > index 3839eef5e4f7..0b957068ff89 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi > > @@ -6,6 +6,10 @@ / { > > compatible = "rockchip,rk3566"; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3566-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>; > > + phy-names = "usb2-phy"; > > + extcon = <&usb2phy0>; > > I wonder what the correct place for this extcon property is. You defined > it on SoC (RK3566) level, in my patch for the RK3568 EVB1 it is added on > board level. Is this common to all RK356x variants? Yes, the usb2phy is always available as an extcon unless you make a device that doesn't have usb2 capability. In that case you'd have to override the device anyways. If we want to turn on default role otg here, we'd need this defined here as well or things break. > > Best regards, > Michael > > > + maximum-speed = "high-speed"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > index 5b0f528d6818..8ba9334f9753 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > > @@ -99,6 +99,10 @@ opp-1992000000 { > > }; > > }; > > > > +&pipegrf { > > + compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > +}; > > + > > &power { > > power-domain@RK3568_PD_PIPE { > > reg = ; > > @@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE { > > #power-domain-cells = <0>; > > }; > > }; > > + > > +&usb_host0_xhci { > > + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > index 7cdef800cb3c..072bb9080cd6 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > @@ -230,6 +230,40 @@ scmi_shmem: sram@0 { > > }; > > }; > > > > + usb_host0_xhci: usb@fcc00000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfcc00000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, > > + <&cru ACLK_USB3OTG0>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG0>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > + usb_host1_xhci: usb@fd000000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xfd000000 0x0 0x400000>; > > + interrupts = ; > > + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, > > + <&cru ACLK_USB3OTG1>; > > + clock-names = "ref_clk", "suspend_clk", > > + "bus_clk"; > > + dr_mode = "host"; > > + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + phy_type = "utmi_wide"; > > + power-domains = <&power RK3568_PD_PIPE>; > > + resets = <&cru SRST_USB3OTG1>; > > + snps,dis_u2_susphy_quirk; > > + status = "disabled"; > > + }; > > + > > gic: interrupt-controller@fd400000 { > > compatible = "arm,gic-v3"; > > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > > @@ -297,7 +331,6 @@ pmu_io_domains: io-domains { > > }; > > > > pipegrf: syscon@fdc50000 { > > - compatible = "rockchip,rk3568-pipe-grf", "syscon"; > > reg = <0x0 0xfdc50000 0x0 0x1000>; > > }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel