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Wed, 26 Jan 2022 12:00:12 -0800 (PST) MIME-Version: 1.0 References: <20220126145549.617165-1-s.hauer@pengutronix.de> <20220126145549.617165-22-s.hauer@pengutronix.de> <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> In-Reply-To: <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> From: Peter Geis Date: Wed, 26 Jan 2022 15:00:01 -0500 Message-ID: Subject: Re: [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes To: Robin Murphy Cc: Sascha Hauer , dri-devel@lists.freedesktop.org, arm-mail-list , "open list:ARM/Rockchip SoC..." , devicetree , kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Michael Riesch , Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jan 26, 2022 at 2:25 PM Robin Murphy wrote: > > On 2022-01-26 18:44, Peter Geis wrote: > > On Wed, Jan 26, 2022 at 12:56 PM Robin Murphy wrote: > >> > >> On 2022-01-26 16:04, Peter Geis wrote: > >>> On Wed, Jan 26, 2022 at 9:58 AM Sascha Hauer wrote: > >>>> > >>>> Add support for the HDMI port found on RK3568. > >>>> > >>>> Signed-off-by: Sascha Hauer > >>>> --- > >>>> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++- > >>>> 1 file changed, 36 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> index 4008bd666d01..e38fb223e9b8 100644 > >>>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> @@ -10,7 +10,6 @@ > >>>> #include > >>>> #include > >>>> #include > >>>> -#include > >>>> #include > >>>> > >>>> / { > >>>> @@ -502,6 +501,42 @@ vop_mmu: iommu@fe043e00 { > >>>> status = "disabled"; > >>>> }; > >>>> > >>>> + hdmi: hdmi@fe0a0000 { > >>>> + compatible = "rockchip,rk3568-dw-hdmi"; > >>>> + reg = <0x0 0xfe0a0000 0x0 0x20000>; > >>>> + interrupts = ; > >>>> + clocks = <&cru PCLK_HDMI_HOST>, > >>>> + <&cru CLK_HDMI_SFR>, > >>>> + <&cru CLK_HDMI_CEC>, > >>>> + <&pmucru CLK_HDMI_REF>, > >>>> + <&cru HCLK_VOP>; > >>>> + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; > >>>> + pinctrl-names = "default"; > >>>> + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; > >>> > >>> I looked into CEC support here, and it seems that it does work with one change. > >>> Please add the two following lines to your patch: > >>> assigned-clocks = <&cru CLK_HDMI_CEC>; > >>> assigned-clock-rates = <32768>; > >>> > >>> The issue is the clk_rtc32k_frac clock that feeds clk_rtc_32k which > >>> feeds clk_hdmi_cec is 24mhz at boot, which is too high for CEC to > >>> function. > >> > >> Wouldn't it make far more sense to just stick a suitable clk_set_rate() > >> call in the driver? AFAICS it's already explicitly aware of the CEC clock. > > > > This is handled purely in the > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c driver, so I'm hesitant to > > touch it there as it would affect all users, not just Rockchip. > > I'd have a strong hunch that it's a standard thing for the DesignWare IP > and not affected by platform integration. I don't have the magical > Synopsys databook, but between the trusty old i.MX6 manual and most of > the other in-tree DTs getting their dw-hdmi "cec" clock from > suspiciously-obviously-named sources, I'd be somewhat surprised if it > was ever anything other than 32KHz. My main concern was similar to the other HDMI clock issues, mainly setting the clock can propagate up and affect other users of the upstream clock. I'll spin up a quick patch for this method. Thanks, Peter > > Robin. > > > Could someone familiar with the dw-hdmi IP weigh in on the minimum and > > maximum clock rate the CEC block can handle? > > > >> > >> Robin. > >> > >>>> + power-domains = <&power RK3568_PD_VO>; > >>>> + reg-io-width = <4>; > >>>> + rockchip,grf = <&grf>; > >>>> + #sound-dai-cells = <0>; > >>>> + status = "disabled"; > >>>> + > >>>> + ports { > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + > >>>> + hdmi_in: port@0 { > >>>> + reg = <0>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + > >>>> + hdmi_out: port@1 { > >>>> + reg = <1>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + }; > >>>> + }; > >>>> + > >>>> qos_gpu: qos@fe128000 { > >>>> compatible = "rockchip,rk3568-qos", "syscon"; > >>>> reg = <0x0 0xfe128000 0x0 0x20>; > >>>> -- > >>>> 2.30.2 > >>>> > >>> > >>> _______________________________________________ > >>> Linux-rockchip mailing list > >>> Linux-rockchip@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31FEDC28CF5 for ; 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bh=wJitFFvuG9U27VE5xDsshWEG+RLx//q3+Kf8s/0efLA=; b=a6avERH8Ymz4tYJYklfWUV6MI1hBDhW0CPrLh2R2TApNvtFfOcXYwcfrvL2Dyoe/lZ 6NAH4VUloLKuFcXiuTH0G2LuqvrQGa+A9/8DuLy0J/Y8qX1gBSarGPyIXB7rpG4ouCAz OqPXujYu/l8pRNvEDST8ypL+lYOrekP0AbqZknOjAz6Utu6IfujYhAU9ZL3XW4Eokmcn uUw40DKXnOjb4KkzdULIRGfDL7CHb7FwZ6/2S0PS89oi+SWHTY0FmPQCar3Qo+K9WBuf lS+sMufWMPCvPWP/DVAJmg9uWlsHB55nsVqFsdmk8jEvmSAjVCczBccCwiHYXHzajAje /80Q== X-Gm-Message-State: AOAM530G8f8oO8s2VNcpeST6xaDYL9XKHw3XZ8QY8awzifkTksgCZ4C5 4xBPNNmQ7w0NZiuiL38EtzR9h/8Vp/Ca2Wy9HQxCzYkFb0Y= X-Google-Smtp-Source: ABdhPJxth+wPVilLzlTzlFktv0sqR193AtoZzoZz1MfcBDy+YaXG320Ay/wnjmM+mLCBKK07QwNqr+YuazBkReA/GNQ= X-Received: by 2002:a25:1583:: with SMTP id 125mr766085ybv.216.1643227212355; Wed, 26 Jan 2022 12:00:12 -0800 (PST) MIME-Version: 1.0 References: <20220126145549.617165-1-s.hauer@pengutronix.de> <20220126145549.617165-22-s.hauer@pengutronix.de> <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> In-Reply-To: <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> From: Peter Geis Date: Wed, 26 Jan 2022 15:00:01 -0500 Message-ID: Subject: Re: [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes To: Robin Murphy Cc: Sascha Hauer , dri-devel@lists.freedesktop.org, arm-mail-list , "open list:ARM/Rockchip SoC..." , devicetree , kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Michael Riesch , Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_120014_028472_633A790B X-CRM114-Status: GOOD ( 32.21 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Wed, Jan 26, 2022 at 2:25 PM Robin Murphy wrote: > > On 2022-01-26 18:44, Peter Geis wrote: > > On Wed, Jan 26, 2022 at 12:56 PM Robin Murphy wrote: > >> > >> On 2022-01-26 16:04, Peter Geis wrote: > >>> On Wed, Jan 26, 2022 at 9:58 AM Sascha Hauer wrote: > >>>> > >>>> Add support for the HDMI port found on RK3568. > >>>> > >>>> Signed-off-by: Sascha Hauer > >>>> --- > >>>> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++- > >>>> 1 file changed, 36 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> index 4008bd666d01..e38fb223e9b8 100644 > >>>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> @@ -10,7 +10,6 @@ > >>>> #include > >>>> #include > >>>> #include > >>>> -#include > >>>> #include > >>>> > >>>> / { > >>>> @@ -502,6 +501,42 @@ vop_mmu: iommu@fe043e00 { > >>>> status = "disabled"; > >>>> }; > >>>> > >>>> + hdmi: hdmi@fe0a0000 { > >>>> + compatible = "rockchip,rk3568-dw-hdmi"; > >>>> + reg = <0x0 0xfe0a0000 0x0 0x20000>; > >>>> + interrupts = ; > >>>> + clocks = <&cru PCLK_HDMI_HOST>, > >>>> + <&cru CLK_HDMI_SFR>, > >>>> + <&cru CLK_HDMI_CEC>, > >>>> + <&pmucru CLK_HDMI_REF>, > >>>> + <&cru HCLK_VOP>; > >>>> + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; > >>>> + pinctrl-names = "default"; > >>>> + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; > >>> > >>> I looked into CEC support here, and it seems that it does work with one change. > >>> Please add the two following lines to your patch: > >>> assigned-clocks = <&cru CLK_HDMI_CEC>; > >>> assigned-clock-rates = <32768>; > >>> > >>> The issue is the clk_rtc32k_frac clock that feeds clk_rtc_32k which > >>> feeds clk_hdmi_cec is 24mhz at boot, which is too high for CEC to > >>> function. > >> > >> Wouldn't it make far more sense to just stick a suitable clk_set_rate() > >> call in the driver? AFAICS it's already explicitly aware of the CEC clock. > > > > This is handled purely in the > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c driver, so I'm hesitant to > > touch it there as it would affect all users, not just Rockchip. > > I'd have a strong hunch that it's a standard thing for the DesignWare IP > and not affected by platform integration. I don't have the magical > Synopsys databook, but between the trusty old i.MX6 manual and most of > the other in-tree DTs getting their dw-hdmi "cec" clock from > suspiciously-obviously-named sources, I'd be somewhat surprised if it > was ever anything other than 32KHz. My main concern was similar to the other HDMI clock issues, mainly setting the clock can propagate up and affect other users of the upstream clock. I'll spin up a quick patch for this method. Thanks, Peter > > Robin. > > > Could someone familiar with the dw-hdmi IP weigh in on the minimum and > > maximum clock rate the CEC block can handle? > > > >> > >> Robin. > >> > >>>> + power-domains = <&power RK3568_PD_VO>; > >>>> + reg-io-width = <4>; > >>>> + rockchip,grf = <&grf>; > >>>> + #sound-dai-cells = <0>; > >>>> + status = "disabled"; > >>>> + > >>>> + ports { > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + > >>>> + hdmi_in: port@0 { > >>>> + reg = <0>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + > >>>> + hdmi_out: port@1 { > >>>> + reg = <1>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + }; > >>>> + }; > >>>> + > >>>> qos_gpu: qos@fe128000 { > >>>> compatible = "rockchip,rk3568-qos", "syscon"; > >>>> reg = <0x0 0xfe128000 0x0 0x20>; > >>>> -- > >>>> 2.30.2 > >>>> > >>> > >>> _______________________________________________ > >>> Linux-rockchip mailing list > >>> Linux-rockchip@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54BD2C28CF5 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wJitFFvuG9U27VE5xDsshWEG+RLx//q3+Kf8s/0efLA=; b=gAcCQS6If5BbaRIOZbDYn/CzbqG14TGNS9GBeynq2QnAwtJxQ7isSEmMwLvhuz6Fcn gqt4X4oiwMysOW9rjh1J37HhACEiYVlYMK6jmtvWI371jYzfb2wpZq08lbTPYLfsuFM3 8dXQw/FPilpeYRcd89op1de6Bsj+HFNPnAbTcHNPymK6YOKqn17GqNtNkBDgDEzaqCx6 hlEfOoDA4JgEe22OQawpdG6jpJlKKSlz7ZAJCiV+lvyJpfBiyoPaKIQVlHzCYAo7tTuI uoPIwoZmbG1xtN0YE7y49cJNcNuxqRCJMbA/5BzW854MlR4ynP6WVhS3d9Td3lZ5mfxU BF0A== X-Gm-Message-State: AOAM533VEUCoEL9Im7dkQ1POolJ7Rgwlp8pYkJpOsctCoqrMr2CHTvgi X58MpdCZyfbr4jUzs6yTqFtQ1u1pC+Gi0n17Yz0= X-Google-Smtp-Source: ABdhPJxth+wPVilLzlTzlFktv0sqR193AtoZzoZz1MfcBDy+YaXG320Ay/wnjmM+mLCBKK07QwNqr+YuazBkReA/GNQ= X-Received: by 2002:a25:1583:: with SMTP id 125mr766085ybv.216.1643227212355; Wed, 26 Jan 2022 12:00:12 -0800 (PST) MIME-Version: 1.0 References: <20220126145549.617165-1-s.hauer@pengutronix.de> <20220126145549.617165-22-s.hauer@pengutronix.de> <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> In-Reply-To: <45132d1f-626d-5fe3-3118-21c0b3f4c8f1@arm.com> From: Peter Geis Date: Wed, 26 Jan 2022 15:00:01 -0500 Message-ID: Subject: Re: [PATCH 21/27] arm64: dts: rockchip: rk356x: Add HDMI nodes To: Robin Murphy Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , Benjamin Gaignard , Sascha Hauer , Sandy Huang , dri-devel@lists.freedesktop.org, "open list:ARM/Rockchip SoC..." , Michael Riesch , kernel@pengutronix.de, Andy Yan , arm-mail-list Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Jan 26, 2022 at 2:25 PM Robin Murphy wrote: > > On 2022-01-26 18:44, Peter Geis wrote: > > On Wed, Jan 26, 2022 at 12:56 PM Robin Murphy wrote: > >> > >> On 2022-01-26 16:04, Peter Geis wrote: > >>> On Wed, Jan 26, 2022 at 9:58 AM Sascha Hauer wrote: > >>>> > >>>> Add support for the HDMI port found on RK3568. > >>>> > >>>> Signed-off-by: Sascha Hauer > >>>> --- > >>>> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++- > >>>> 1 file changed, 36 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> index 4008bd666d01..e38fb223e9b8 100644 > >>>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> @@ -10,7 +10,6 @@ > >>>> #include > >>>> #include > >>>> #include > >>>> -#include > >>>> #include > >>>> > >>>> / { > >>>> @@ -502,6 +501,42 @@ vop_mmu: iommu@fe043e00 { > >>>> status = "disabled"; > >>>> }; > >>>> > >>>> + hdmi: hdmi@fe0a0000 { > >>>> + compatible = "rockchip,rk3568-dw-hdmi"; > >>>> + reg = <0x0 0xfe0a0000 0x0 0x20000>; > >>>> + interrupts = ; > >>>> + clocks = <&cru PCLK_HDMI_HOST>, > >>>> + <&cru CLK_HDMI_SFR>, > >>>> + <&cru CLK_HDMI_CEC>, > >>>> + <&pmucru CLK_HDMI_REF>, > >>>> + <&cru HCLK_VOP>; > >>>> + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; > >>>> + pinctrl-names = "default"; > >>>> + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; > >>> > >>> I looked into CEC support here, and it seems that it does work with one change. > >>> Please add the two following lines to your patch: > >>> assigned-clocks = <&cru CLK_HDMI_CEC>; > >>> assigned-clock-rates = <32768>; > >>> > >>> The issue is the clk_rtc32k_frac clock that feeds clk_rtc_32k which > >>> feeds clk_hdmi_cec is 24mhz at boot, which is too high for CEC to > >>> function. > >> > >> Wouldn't it make far more sense to just stick a suitable clk_set_rate() > >> call in the driver? AFAICS it's already explicitly aware of the CEC clock. > > > > This is handled purely in the > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c driver, so I'm hesitant to > > touch it there as it would affect all users, not just Rockchip. > > I'd have a strong hunch that it's a standard thing for the DesignWare IP > and not affected by platform integration. I don't have the magical > Synopsys databook, but between the trusty old i.MX6 manual and most of > the other in-tree DTs getting their dw-hdmi "cec" clock from > suspiciously-obviously-named sources, I'd be somewhat surprised if it > was ever anything other than 32KHz. My main concern was similar to the other HDMI clock issues, mainly setting the clock can propagate up and affect other users of the upstream clock. I'll spin up a quick patch for this method. Thanks, Peter > > Robin. > > > Could someone familiar with the dw-hdmi IP weigh in on the minimum and > > maximum clock rate the CEC block can handle? > > > >> > >> Robin. > >> > >>>> + power-domains = <&power RK3568_PD_VO>; > >>>> + reg-io-width = <4>; > >>>> + rockchip,grf = <&grf>; > >>>> + #sound-dai-cells = <0>; > >>>> + status = "disabled"; > >>>> + > >>>> + ports { > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + > >>>> + hdmi_in: port@0 { > >>>> + reg = <0>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + > >>>> + hdmi_out: port@1 { > >>>> + reg = <1>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + }; > >>>> + }; > >>>> + > >>>> qos_gpu: qos@fe128000 { > >>>> compatible = "rockchip,rk3568-qos", "syscon"; > >>>> reg = <0x0 0xfe128000 0x0 0x20>; > >>>> -- > >>>> 2.30.2 > >>>> > >>> > >>> _______________________________________________ > >>> Linux-rockchip mailing list > >>> Linux-rockchip@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9299C28CF5 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 26, 2022 at 2:25 PM Robin Murphy wrote: > > On 2022-01-26 18:44, Peter Geis wrote: > > On Wed, Jan 26, 2022 at 12:56 PM Robin Murphy wrote: > >> > >> On 2022-01-26 16:04, Peter Geis wrote: > >>> On Wed, Jan 26, 2022 at 9:58 AM Sascha Hauer wrote: > >>>> > >>>> Add support for the HDMI port found on RK3568. > >>>> > >>>> Signed-off-by: Sascha Hauer > >>>> --- > >>>> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++- > >>>> 1 file changed, 36 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> index 4008bd666d01..e38fb223e9b8 100644 > >>>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > >>>> @@ -10,7 +10,6 @@ > >>>> #include > >>>> #include > >>>> #include > >>>> -#include > >>>> #include > >>>> > >>>> / { > >>>> @@ -502,6 +501,42 @@ vop_mmu: iommu@fe043e00 { > >>>> status = "disabled"; > >>>> }; > >>>> > >>>> + hdmi: hdmi@fe0a0000 { > >>>> + compatible = "rockchip,rk3568-dw-hdmi"; > >>>> + reg = <0x0 0xfe0a0000 0x0 0x20000>; > >>>> + interrupts = ; > >>>> + clocks = <&cru PCLK_HDMI_HOST>, > >>>> + <&cru CLK_HDMI_SFR>, > >>>> + <&cru CLK_HDMI_CEC>, > >>>> + <&pmucru CLK_HDMI_REF>, > >>>> + <&cru HCLK_VOP>; > >>>> + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; > >>>> + pinctrl-names = "default"; > >>>> + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; > >>> > >>> I looked into CEC support here, and it seems that it does work with one change. > >>> Please add the two following lines to your patch: > >>> assigned-clocks = <&cru CLK_HDMI_CEC>; > >>> assigned-clock-rates = <32768>; > >>> > >>> The issue is the clk_rtc32k_frac clock that feeds clk_rtc_32k which > >>> feeds clk_hdmi_cec is 24mhz at boot, which is too high for CEC to > >>> function. > >> > >> Wouldn't it make far more sense to just stick a suitable clk_set_rate() > >> call in the driver? AFAICS it's already explicitly aware of the CEC clock. > > > > This is handled purely in the > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c driver, so I'm hesitant to > > touch it there as it would affect all users, not just Rockchip. > > I'd have a strong hunch that it's a standard thing for the DesignWare IP > and not affected by platform integration. I don't have the magical > Synopsys databook, but between the trusty old i.MX6 manual and most of > the other in-tree DTs getting their dw-hdmi "cec" clock from > suspiciously-obviously-named sources, I'd be somewhat surprised if it > was ever anything other than 32KHz. My main concern was similar to the other HDMI clock issues, mainly setting the clock can propagate up and affect other users of the upstream clock. I'll spin up a quick patch for this method. Thanks, Peter > > Robin. > > > Could someone familiar with the dw-hdmi IP weigh in on the minimum and > > maximum clock rate the CEC block can handle? > > > >> > >> Robin. > >> > >>>> + power-domains = <&power RK3568_PD_VO>; > >>>> + reg-io-width = <4>; > >>>> + rockchip,grf = <&grf>; > >>>> + #sound-dai-cells = <0>; > >>>> + status = "disabled"; > >>>> + > >>>> + ports { > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + > >>>> + hdmi_in: port@0 { > >>>> + reg = <0>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + > >>>> + hdmi_out: port@1 { > >>>> + reg = <1>; > >>>> + #address-cells = <1>; > >>>> + #size-cells = <0>; > >>>> + }; > >>>> + }; > >>>> + }; > >>>> + > >>>> qos_gpu: qos@fe128000 { > >>>> compatible = "rockchip,rk3568-qos", "syscon"; > >>>> reg = <0x0 0xfe128000 0x0 0x20>; > >>>> -- > >>>> 2.30.2 > >>>> > >>> > >>> _______________________________________________ > >>> Linux-rockchip mailing list > >>> Linux-rockchip@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel