From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B27C4338F for ; Mon, 9 Aug 2021 10:58:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 84B1A61078 for ; Mon, 9 Aug 2021 10:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234859AbhHIK63 (ORCPT ); Mon, 9 Aug 2021 06:58:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233496AbhHIK6S (ORCPT ); Mon, 9 Aug 2021 06:58:18 -0400 Received: from mail-yb1-xb34.google.com (mail-yb1-xb34.google.com [IPv6:2607:f8b0:4864:20::b34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11AC7C0613D3; Mon, 9 Aug 2021 03:57:50 -0700 (PDT) Received: by mail-yb1-xb34.google.com with SMTP id c137so28270339ybf.5; Mon, 09 Aug 2021 03:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=29y/iLxNFNnvLYgOgqntrEvNskLkzb3T+cHZyF7bUPo=; b=Abm0cm6I/+CyTKXMwu6hEStFtMK0RXqgvqMbDOU/bH56Ibe53b1hnHrCED8JjLC51E FuEsvn9kUgt7XKG2dGVuq0RFAivZ3D8b/WEMs30oyTvoCZN8vkxzcSXzzxZ8d3Qo++Au znyFDhAK2894pPpwut/GtMhzTJTCfM08naRZMqmAW+0QXj+s511h06x48j7oFq8GKTT0 3HlzxlTe8RpL55FsYZyNR0/kpfW4F6qHG9BNc5P6uvui74Cfulrj77qQi2CzO3Mj9vIC QGk+kN7D2AmTLvjikUV4Uf+PwYfbYrNESCZWBc/fAX1WYFJMe2r49iEGnj2BEIDJE6Zx 9SRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=29y/iLxNFNnvLYgOgqntrEvNskLkzb3T+cHZyF7bUPo=; b=k0NP7ArG3Iz1RgzZB6dKyEnp2dqXEEt6mXoI6QuDiTQ83hPycxW4npYl6EWy1lu2A0 6Cv72EvkdJXcYRjPQ4f4S41gmr7ps/pIXpYMyJ6EEd5cyHriBTyeXyTP1AYJoPitnwgP D6nfd5f7EMm7Xhco7eL8lHmo3Xxe44mC1RJs7R8wN3Mf1zP+dMtlSmPXcpBWuZ4Df7kR MkJBT9u7UL66m6jNATnqcKavsZw0SI6JXG1lJvGtKfioswhUiy3Ix9Wxe28EhXwG5fxC wYm2NxgI+LbcNlNb9Y1VLKI80hbW3nOK7WZTtuYvKzorirYyEt+gG0FUqRG90NSfjwZN L0MA== X-Gm-Message-State: AOAM531IwqO06EnADMk7z+kLILhj8wGdmQ7M0sVd7K6Je5sb9nQ38VOD 7oiMVFhVt64C2uFkq0kJIemXgbaxYxO9vP2Q6rM= X-Google-Smtp-Source: ABdhPJyIaGIL719GmPBLn0xZ+eSUsLKZMW2KPqAsrxqSHsss+LR1j4yGTNSE/bVQW/GmAV7DPoLWWnaPvdWwoWs45oY= X-Received: by 2002:a25:3c5:: with SMTP id 188mr28131568ybd.437.1628506669209; Mon, 09 Aug 2021 03:57:49 -0700 (PDT) MIME-Version: 1.0 References: <20210625065511.1096935-1-xxm@rock-chips.com> <202108091743281185811@rock-chips.com> In-Reply-To: <202108091743281185811@rock-chips.com> From: Peter Geis Date: Mon, 9 Aug 2021 06:57:38 -0400 Message-ID: Subject: Re: [PATCH v11] PCI: rockchip-dwc: Add Rockchip RK356X host controller driver To: "xxm@rock-chips.com" Cc: Bjorn Helgaas , Lorenzo Pieralisi , linux-pci , linux-rockchip , devicetree , "robh+dt" , jbx6244 , heiko , "kever.yang" , =?UTF-8?B?5p6X5rabKOW6leWxguW5s+WPsCk=?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Aug 9, 2021 at 5:43 AM xxm@rock-chips.com wrot= e: > > Hi all, > > If any new comments about this patch? Good Morning, Not a direct comment, but certainly adjacent. Is there any status on the ITS errata? My reasoning is the mbi-alias method isn't perfect, for example the following error is constantlyseen using it: [39910.458531] ixgbe 0000:01:00.1 enp1s0f1: NIC Link is Up 10 Gbps, Flow Control: RX/TX [40049.195579] ixgbe 0000:01:00.1 enp1s0f1: NIC Link is Down [40049.783010] ixgbe 0000:01:00.1 enp1s0f1: NIC Link is Up 10 Gbps, Flow Control: RX/TX [40110.597421] ixgbe 0000:01:00.1 enp1s0f1: NIC Link is Down This issue doesn't occur when using legacy interrupts nor proper ITS servic= es. The only other issue I have encountered is dGPUs do not function. I suspect the PCIe controller is affected by the same cache coherency issue as the ITS translator is, is that correct? Otherwise, I've had great success with this driver. Very Respectfully, Peter Geis > >Add a driver for the DesignWare-based PCIe controller found on > >RK356X. The existing pcie-rockchip-host driver is only used for > >the Rockchip-designed IP found on RK3399. > > > >Tested-by: Peter Geis > >Reviewed-by: Kever Yang > >Signed-off-by: Simon Xue > >Signed-off-by: Shawn Lin > >--- > > drivers/pci/controller/dwc/Kconfig | 11 + > > drivers/pci/controller/dwc/Makefile | 1 + > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 276 ++++++++++++++++++ > > 3 files changed, 288 insertions(+) > > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > > >diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller= /dwc/Kconfig > >index 423d35872ce4..60d3dde9ca39 100644 > >--- a/drivers/pci/controller/dwc/Kconfig > >+++ b/drivers/pci/controller/dwc/Kconfig > >@@ -214,6 +214,17 @@ config PCIE_ARTPEC6_EP > > Enables support for the PCIe controller in the ARTPEC-6 SoC to work i= n > > endpoint mode. This uses the DesignWare core. > > > >+config PCIE_ROCKCHIP_DW_HOST > >+ bool "Rockchip DesignWare PCIe controller" > >+ select PCIE_DW > >+ select PCIE_DW_HOST > >+ depends on PCI_MSI_IRQ_DOMAIN > >+ depends on ARCH_ROCKCHIP || COMPILE_TEST > >+ depends on OF > >+ help > >+ Enables support for the DesignWare PCIe controller in the > >+ Rockchip SoC except RK3399. > >+ > > config PCIE_INTEL_GW > > bool "Intel Gateway PCIe host controller support" > > depends on OF && (X86 || COMPILE_TEST) > >diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controlle= r/dwc/Makefile > >index 9e6ce0dc2f53..3710e91471f7 100644 > >--- a/drivers/pci/controller/dwc/Makefile > >+++ b/drivers/pci/controller/dwc/Makefile > >@@ -14,6 +14,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) +=3D pci-layerscape-ep= .o > > obj-$(CONFIG_PCIE_QCOM) +=3D pcie-qcom.o > > obj-$(CONFIG_PCIE_ARMADA_8K) +=3D pcie-armada8k.o > > obj-$(CONFIG_PCIE_ARTPEC6) +=3D pcie-artpec6.o > >+obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) +=3D pcie-dw-rockchip.o > > obj-$(CONFIG_PCIE_INTEL_GW) +=3D pcie-intel-gw.o > > obj-$(CONFIG_PCIE_KIRIN) +=3D pcie-kirin.o > > obj-$(CONFIG_PCIE_HISI_STB) +=3D pcie-histb.o > >diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci= /controller/dwc/pcie-dw-rockchip.c > >new file mode 100644 > >index 000000000000..20cef2e06f66 > >--- /dev/null > >+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > >@@ -0,0 +1,276 @@ > >+// SPDX-License-Identifier: GPL-2.0 > >+/* > >+ * PCIe host controller driver for Rockchip SoCs. > >+ * > >+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > >+ * http://www.rock-chips.com > >+ * > >+ * Author: Simon Xue > >+ */ > >+ > >+#include > >+#include > >+#include > >+#include > >+#include > >+#include > >+#include > >+#include > >+#include > >+ > >+#include "pcie-designware.h" > >+ > >+/* > >+ * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > >+ * mask for the lower 16 bits. > >+ */ > >+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) > >+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) > >+ > >+#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) > >+ > >+#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > >+#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > >+#define PCIE_SMLH_LINKUP BIT(16) > >+#define PCIE_RDLH_LINKUP BIT(17) > >+#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > >+#define PCIE_L0S_ENTRY 0x11 > >+#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > >+#define PCIE_CLIENT_GENERAL_DEBUG 0x104 > >+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 > >+#define PCIE_CLIENT_LTSSM_STATUS 0x300 > >+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > >+#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) > >+ > >+struct rockchip_pcie { > >+ struct dw_pcie pci; > >+ void __iomem *apb_base; > >+ struct phy *phy; > >+ struct clk_bulk_data *clks; > >+ unsigned int clk_cnt; > >+ struct reset_control *rst; > >+ struct gpio_desc *rst_gpio; > >+ struct regulator *vpcie3v3; > >+}; > >+ > >+static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, > >+ u32 reg) > >+{ > >+ return readl_relaxed(rockchip->apb_base + reg); > >+} > >+ > >+static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, > >+ u32 val, u32 reg) > >+{ > >+ writel_relaxed(val, rockchip->apb_base + reg); > >+} > >+ > >+static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) > >+{ > >+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, > >+ PCIE_CLIENT_GENERAL_CONTROL); > >+} > >+ > >+static int rockchip_pcie_link_up(struct dw_pcie *pci) > >+{ > >+ struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > >+ u32 val =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_S= TATUS); > >+ > >+ if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP && > >+ (val & PCIE_LTSSM_STATUS_MASK) =3D=3D PCIE_L0S_ENTRY) > >+ return 1; > >+ > >+ return 0; > >+} > >+ > >+static int rockchip_pcie_start_link(struct dw_pcie *pci) > >+{ > >+ struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > >+ > >+ /* Reset device */ > >+ gpiod_set_value_cansleep(rockchip->rst_gpio, 0); > >+ > >+ rockchip_pcie_enable_ltssm(rockchip); > >+ > >+ /* > >+ * PCIe requires the refclk to be stable for 100=C2=B5s prior to r= eleasing > >+ * PERST. See table 2-4 in section 2.6.2 AC Specifications of the = PCI > >+ * Express Card Electromechanical Specification, 1.1. However, we = don't > >+ * know if the refclk is coming from RC's PHY or external OSC. If = it's > >+ * from RC, so enabling LTSSM is the just right place to release #= PERST. > >+ * We need more extra time as before, rather than setting just > >+ * 100us as we don't know how long should the device need to reset= . > >+ */ > >+ msleep(100); > >+ gpiod_set_value_cansleep(rockchip->rst_gpio, 1); > >+ > >+ return 0; > >+} > >+ > >+static int rockchip_pcie_host_init(struct pcie_port *pp) > >+{ > >+ struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); > >+ struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > >+ u32 val =3D HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); > >+ > >+ /* LTSSM enable control mode */ > >+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTR= L); > >+ > >+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, > >+ PCIE_CLIENT_GENERAL_CONTROL); > >+ > >+ return 0; > >+} > >+ > >+static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { > >+ .host_init =3D rockchip_pcie_host_init, > >+}; > >+ > >+static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) > >+{ > >+ struct device *dev =3D rockchip->pci.dev; > >+ int ret; > >+ > >+ ret =3D devm_clk_bulk_get_all(dev, &rockchip->clks); > >+ if (ret < 0) > >+ return ret; > >+ > >+ rockchip->clk_cnt =3D ret; > >+ > >+ return clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks)= ; > >+} > >+ > >+static int rockchip_pcie_resource_get(struct platform_device *pdev, > >+ struct rockchip_pcie *rockchip) > >+{ > >+ rockchip->apb_base =3D devm_platform_ioremap_resource_byname(pdev= , "apb"); > >+ if (IS_ERR(rockchip->apb_base)) > >+ return PTR_ERR(rockchip->apb_base); > >+ > >+ rockchip->rst_gpio =3D devm_gpiod_get_optional(&pdev->dev, "reset= ", > >+ GPIOD_OUT_HIGH); > >+ if (IS_ERR(rockchip->rst_gpio)) > >+ return PTR_ERR(rockchip->rst_gpio); > >+ > >+ return 0; > >+} > >+ > >+static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip) > >+{ > >+ struct device *dev =3D rockchip->pci.dev; > >+ int ret; > >+ > >+ rockchip->phy =3D devm_phy_get(dev, "pcie-phy"); > >+ if (IS_ERR(rockchip->phy)) > >+ return dev_err_probe(dev, PTR_ERR(rockchip->phy), > >+ "missing PHY\n"); > >+ > >+ ret =3D phy_init(rockchip->phy); > >+ if (ret < 0) > >+ return ret; > >+ > >+ ret =3D phy_power_on(rockchip->phy); > >+ if (ret) > >+ phy_exit(rockchip->phy); > >+ > >+ return ret; > >+} > >+ > >+static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) > >+{ > >+ phy_exit(rockchip->phy); > >+ phy_power_off(rockchip->phy); > >+} > >+ > >+static int rockchip_pcie_reset_control_release(struct rockchip_pcie *ro= ckchip) > >+{ > >+ struct device *dev =3D rockchip->pci.dev; > >+ > >+ rockchip->rst =3D devm_reset_control_array_get_exclusive(dev); > >+ if (IS_ERR(rockchip->rst)) > >+ return dev_err_probe(dev, PTR_ERR(rockchip->rst), > >+ "failed to get reset lines\n"); > >+ > >+ return reset_control_deassert(rockchip->rst); > >+} > >+ > >+static const struct dw_pcie_ops dw_pcie_ops =3D { > >+ .link_up =3D rockchip_pcie_link_up, > >+ .start_link =3D rockchip_pcie_start_link, > >+}; > >+ > >+static int rockchip_pcie_probe(struct platform_device *pdev) > >+{ > >+ struct device *dev =3D &pdev->dev; > >+ struct rockchip_pcie *rockchip; > >+ struct pcie_port *pp; > >+ int ret; > >+ > >+ rockchip =3D devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); > >+ if (!rockchip) > >+ return -ENOMEM; > >+ > >+ platform_set_drvdata(pdev, rockchip); > >+ > >+ rockchip->pci.dev =3D dev; > >+ rockchip->pci.ops =3D &dw_pcie_ops; > >+ > >+ pp =3D &rockchip->pci.pp; > >+ pp->ops =3D &rockchip_pcie_host_ops; > >+ > >+ ret =3D rockchip_pcie_resource_get(pdev, rockchip); > >+ if (ret) > >+ return ret; > >+ > >+ /* DON'T MOVE ME: must be enable before PHY init */ > >+ rockchip->vpcie3v3 =3D devm_regulator_get_optional(dev, "vpcie3v3= "); > >+ if (IS_ERR(rockchip->vpcie3v3)) > >+ if (PTR_ERR(rockchip->vpcie3v3) !=3D -ENODEV) > >+ return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3), > >+ "failed to get vpcie3v3 regulator\n"); > >+ > >+ ret =3D regulator_enable(rockchip->vpcie3v3); > >+ if (ret) { > >+ dev_err(dev, "failed to enable vpcie3v3 regulator\n"); > >+ return ret; > >+ } > >+ > >+ ret =3D rockchip_pcie_phy_init(rockchip); > >+ if (ret) > >+ goto disable_regulator; > >+ > >+ ret =3D rockchip_pcie_reset_control_release(rockchip); > >+ if (ret) > >+ goto deinit_phy; > >+ > >+ ret =3D rockchip_pcie_clk_init(rockchip); > >+ if (ret) > >+ goto deinit_phy; > >+ > >+ ret =3D dw_pcie_host_init(pp); > >+ if (!ret) > >+ return 0; > >+ > >+ clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); > >+deinit_phy: > >+ rockchip_pcie_phy_deinit(rockchip); > >+disable_regulator: > >+ regulator_disable(rockchip->vpcie3v3); > >+ > >+ return ret; > >+} > >+ > >+static const struct of_device_id rockchip_pcie_of_match[] =3D { > >+ { .compatible =3D "rockchip,rk3568-pcie", }, > >+ {}, > >+}; > >+ > >+static struct platform_driver rockchip_pcie_driver =3D { > >+ .driver =3D { > >+ .name =3D "rockchip-dw-pcie", > >+ .of_match_table =3D rockchip_pcie_of_match, > >+ .suppress_bind_attrs =3D true, > >+ }, > >+ .probe =3D rockchip_pcie_probe, > >+}; > >+builtin_platform_driver(rockchip_pcie_driver); > >-- > >2.25.1 > > > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 340E6C4338F for ; Mon, 9 Aug 2021 10:58:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher 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MR-646709E3 X-CRM114-CacheID: sfid-20210809_035751_222898_C6A52599 X-CRM114-Status: GOOD ( 30.29 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org T24gTW9uLCBBdWcgOSwgMjAyMSBhdCA1OjQzIEFNIHh4bUByb2NrLWNoaXBzLmNvbSA8eHhtQHJv Y2stY2hpcHMuY29tPiB3cm90ZToKPgo+IEhpIGFsbCwKPgo+IElmIGFueSBuZXcgY29tbWVudHMg YWJvdXQgdGhpcyBwYXRjaD8KCkdvb2QgTW9ybmluZywKCk5vdCBhIGRpcmVjdCBjb21tZW50LCBi dXQgY2VydGFpbmx5IGFkamFjZW50LgpJcyB0aGVyZSBhbnkgc3RhdHVzIG9uIHRoZSBJVFMgZXJy YXRhPwoKTXkgcmVhc29uaW5nIGlzIHRoZSBtYmktYWxpYXMgbWV0aG9kIGlzbid0IHBlcmZlY3Qs IGZvciBleGFtcGxlIHRoZQpmb2xsb3dpbmcgZXJyb3IgaXMgY29uc3RhbnRseXNlZW4gdXNpbmcg aXQ6ClszOTkxMC40NTg1MzFdIGl4Z2JlIDAwMDA6MDE6MDAuMSBlbnAxczBmMTogTklDIExpbmsg aXMgVXAgMTAgR2JwcywKRmxvdyBDb250cm9sOiBSWC9UWApbNDAwNDkuMTk1NTc5XSBpeGdiZSAw MDAwOjAxOjAwLjEgZW5wMXMwZjE6IE5JQyBMaW5rIGlzIERvd24KWzQwMDQ5Ljc4MzAxMF0gaXhn YmUgMDAwMDowMTowMC4xIGVucDFzMGYxOiBOSUMgTGluayBpcyBVcCAxMCBHYnBzLApGbG93IENv bnRyb2w6IFJYL1RYCls0MDExMC41OTc0MjFdIGl4Z2JlIDAwMDA6MDE6MDAuMSBlbnAxczBmMTog TklDIExpbmsgaXMgRG93bgoKVGhpcyBpc3N1ZSBkb2Vzbid0IG9jY3VyIHdoZW4gdXNpbmcgbGVn YWN5IGludGVycnVwdHMgbm9yIHByb3BlciBJVFMgc2VydmljZXMuCgpUaGUgb25seSBvdGhlciBp c3N1ZSBJIGhhdmUgZW5jb3VudGVyZWQgaXMgZEdQVXMgZG8gbm90IGZ1bmN0aW9uLgpJIHN1c3Bl Y3QgdGhlIFBDSWUgY29udHJvbGxlciBpcyBhZmZlY3RlZCBieSB0aGUgc2FtZSBjYWNoZSBjb2hl cmVuY3kKaXNzdWUgYXMgdGhlIElUUyB0cmFuc2xhdG9yIGlzLCBpcyB0aGF0IGNvcnJlY3Q/CgpP dGhlcndpc2UsIEkndmUgaGFkIGdyZWF0IHN1Y2Nlc3Mgd2l0aCB0aGlzIGRyaXZlci4KClZlcnkg UmVzcGVjdGZ1bGx5LApQZXRlciBHZWlzCgo+ID5BZGQgYSBkcml2ZXIgZm9yIHRoZSBEZXNpZ25X YXJlLWJhc2VkIFBDSWUgY29udHJvbGxlciBmb3VuZCBvbgo+ID5SSzM1NlguIFRoZSBleGlzdGlu ZyBwY2llLXJvY2tjaGlwLWhvc3QgZHJpdmVyIGlzIG9ubHkgdXNlZCBmb3IKPiA+dGhlIFJvY2tj aGlwLWRlc2lnbmVkIElQIGZvdW5kIG9uIFJLMzM5OS4KPiA+Cj4gPlRlc3RlZC1ieTogUGV0ZXIg R2VpcyA8cGd3aXBlb3V0QGdtYWlsLmNvbT4KPiA+UmV2aWV3ZWQtYnk6IEtldmVyIFlhbmcgPGtl dmVyLnlhbmdAcm9jay1jaGlwcy5jb20+Cj4gPlNpZ25lZC1vZmYtYnk6IFNpbW9uIFh1ZSA8eHht QHJvY2stY2hpcHMuY29tPgo+ID5TaWduZWQtb2ZmLWJ5OiBTaGF3biBMaW4gPHNoYXduLmxpbkBy b2NrLWNoaXBzLmNvbT4KPiA+LS0tCj4gPiBkcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9LY29u ZmlnICAgICAgICAgICAgfCAgMTEgKwo+ID4gZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvTWFr ZWZpbGUgICAgICAgICAgIHwgICAxICsKPiA+IGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3Bj aWUtZHctcm9ja2NoaXAuYyB8IDI3NiArKysrKysrKysrKysrKysrKysKPiA+IDMgZmlsZXMgY2hh bmdlZCwgMjg4IGluc2VydGlvbnMoKykKPiA+IGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3Bj aS9jb250cm9sbGVyL2R3Yy9wY2llLWR3LXJvY2tjaGlwLmMKPiA+Cj4gPmRpZmYgLS1naXQgYS9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9LY29uZmlnIGIvZHJpdmVycy9wY2kvY29udHJvbGxl ci9kd2MvS2NvbmZpZwo+ID5pbmRleCA0MjNkMzU4NzJjZTQuLjYwZDNkZGU5Y2EzOSAxMDA2NDQK PiA+LS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvS2NvbmZpZwo+ID4rKysgYi9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9LY29uZmlnCj4gPkBAIC0yMTQsNiArMjE0LDE3IEBAIGNv bmZpZyBQQ0lFX0FSVFBFQzZfRVAKPiA+ICAgRW5hYmxlcyBzdXBwb3J0IGZvciB0aGUgUENJZSBj b250cm9sbGVyIGluIHRoZSBBUlRQRUMtNiBTb0MgdG8gd29yayBpbgo+ID4gICBlbmRwb2ludCBt b2RlLiBUaGlzIHVzZXMgdGhlIERlc2lnbldhcmUgY29yZS4KPiA+Cj4gPitjb25maWcgUENJRV9S T0NLQ0hJUF9EV19IT1NUCj4gPisgICAgICBib29sICJSb2NrY2hpcCBEZXNpZ25XYXJlIFBDSWUg Y29udHJvbGxlciIKPiA+KyAgICAgIHNlbGVjdCBQQ0lFX0RXCj4gPisgICAgICBzZWxlY3QgUENJ RV9EV19IT1NUCj4gPisgICAgICBkZXBlbmRzIG9uIFBDSV9NU0lfSVJRX0RPTUFJTgo+ID4rICAg ICAgZGVwZW5kcyBvbiBBUkNIX1JPQ0tDSElQIHx8IENPTVBJTEVfVEVTVAo+ID4rICAgICAgZGVw ZW5kcyBvbiBPRgo+ID4rICAgICAgaGVscAo+ID4rICAgICAgICBFbmFibGVzIHN1cHBvcnQgZm9y IHRoZSBEZXNpZ25XYXJlIFBDSWUgY29udHJvbGxlciBpbiB0aGUKPiA+KyAgICAgICAgUm9ja2No aXAgU29DIGV4Y2VwdCBSSzMzOTkuCj4gPisKPiA+IGNvbmZpZyBQQ0lFX0lOVEVMX0dXCj4gPiBi b29sICJJbnRlbCBHYXRld2F5IFBDSWUgaG9zdCBjb250cm9sbGVyIHN1cHBvcnQiCj4gPiBkZXBl bmRzIG9uIE9GICYmIChYODYgfHwgQ09NUElMRV9URVNUKQo+ID5kaWZmIC0tZ2l0IGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvTWFrZWZpbGUgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3 Yy9NYWtlZmlsZQo+ID5pbmRleCA5ZTZjZTBkYzJmNTMuLjM3MTBlOTE0NzFmNyAxMDA2NDQKPiA+ LS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvTWFrZWZpbGUKPiA+KysrIGIvZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvTWFrZWZpbGUKPiA+QEAgLTE0LDYgKzE0LDcgQEAgb2JqLSQo Q09ORklHX1BDSV9MQVlFUlNDQVBFX0VQKSArPSBwY2ktbGF5ZXJzY2FwZS1lcC5vCj4gPiBvYmot JChDT05GSUdfUENJRV9RQ09NKSArPSBwY2llLXFjb20ubwo+ID4gb2JqLSQoQ09ORklHX1BDSUVf QVJNQURBXzhLKSArPSBwY2llLWFybWFkYThrLm8KPiA+IG9iai0kKENPTkZJR19QQ0lFX0FSVFBF QzYpICs9IHBjaWUtYXJ0cGVjNi5vCj4gPitvYmotJChDT05GSUdfUENJRV9ST0NLQ0hJUF9EV19I T1NUKSArPSBwY2llLWR3LXJvY2tjaGlwLm8KPiA+IG9iai0kKENPTkZJR19QQ0lFX0lOVEVMX0dX KSArPSBwY2llLWludGVsLWd3Lm8KPiA+IG9iai0kKENPTkZJR19QQ0lFX0tJUklOKSArPSBwY2ll LWtpcmluLm8KPiA+IG9iai0kKENPTkZJR19QQ0lFX0hJU0lfU1RCKSArPSBwY2llLWhpc3RiLm8K PiA+ZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZHctcm9ja2No aXAuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZHctcm9ja2NoaXAuYwo+ID5u ZXcgZmlsZSBtb2RlIDEwMDY0NAo+ID5pbmRleCAwMDAwMDAwMDAwMDAuLjIwY2VmMmUwNmY2Ngo+ ID4tLS0gL2Rldi9udWxsCj4gPisrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUt ZHctcm9ja2NoaXAuYwo+ID5AQCAtMCwwICsxLDI3NiBAQAo+ID4rLy8gU1BEWC1MaWNlbnNlLUlk ZW50aWZpZXI6IEdQTC0yLjAKPiA+Ky8qCj4gPisgKiBQQ0llIGhvc3QgY29udHJvbGxlciBkcml2 ZXIgZm9yIFJvY2tjaGlwIFNvQ3MuCj4gPisgKgo+ID4rICogQ29weXJpZ2h0IChDKSAyMDIxIFJv Y2tjaGlwIEVsZWN0cm9uaWNzIENvLiwgTHRkLgo+ID4rICogICAgaHR0cDovL3d3dy5yb2NrLWNo aXBzLmNvbQo+ID4rICoKPiA+KyAqIEF1dGhvcjogU2ltb24gWHVlIDx4eG1Acm9jay1jaGlwcy5j b20+Cj4gPisgKi8KPiA+Kwo+ID4rI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgo+ID4rI2luY2x1ZGUg PGxpbnV4L2dwaW8vY29uc3VtZXIuaD4KPiA+KyNpbmNsdWRlIDxsaW51eC9tZmQvc3lzY29uLmg+ Cj4gPisjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPisjaW5jbHVkZSA8bGludXgvb2ZfZGV2 aWNlLmg+Cj4gPisjaW5jbHVkZSA8bGludXgvcGh5L3BoeS5oPgo+ID4rI2luY2x1ZGUgPGxpbnV4 L3BsYXRmb3JtX2RldmljZS5oPgo+ID4rI2luY2x1ZGUgPGxpbnV4L3JlZ21hcC5oPgo+ID4rI2lu Y2x1ZGUgPGxpbnV4L3Jlc2V0Lmg+Cj4gPisKPiA+KyNpbmNsdWRlICJwY2llLWRlc2lnbndhcmUu aCIKPiA+Kwo+ID4rLyoKPiA+KyAqIFRoZSB1cHBlciAxNiBiaXRzIG9mIFBDSUVfQ0xJRU5UX0NP TkZJRyBhcmUgYSB3cml0ZQo+ID4rICogbWFzayBmb3IgdGhlIGxvd2VyIDE2IGJpdHMuCj4gPisg Ki8KPiA+KyNkZWZpbmUgSElXT1JEX1VQREFURShtYXNrLCB2YWwpICgoKG1hc2spIDw8IDE2KSB8 ICh2YWwpKQo+ID4rI2RlZmluZSBISVdPUkRfVVBEQVRFX0JJVCh2YWwpICAgICAgICBISVdPUkRf VVBEQVRFKHZhbCwgdmFsKQo+ID4rCj4gPisjZGVmaW5lIHRvX3JvY2tjaGlwX3BjaWUoeCkgZGV2 X2dldF9kcnZkYXRhKCh4KS0+ZGV2KQo+ID4rCj4gPisjZGVmaW5lIFBDSUVfQ0xJRU5UX1JDX01P REUgICBISVdPUkRfVVBEQVRFX0JJVCgweDQwKQo+ID4rI2RlZmluZSBQQ0lFX0NMSUVOVF9FTkFC TEVfTFRTU00gICAgICBISVdPUkRfVVBEQVRFX0JJVCgweGMpCj4gPisjZGVmaW5lIFBDSUVfU01M SF9MSU5LVVAgICAgICBCSVQoMTYpCj4gPisjZGVmaW5lIFBDSUVfUkRMSF9MSU5LVVAgICAgICBC SVQoMTcpCj4gPisjZGVmaW5lIFBDSUVfTElOS1VQICAgKFBDSUVfU01MSF9MSU5LVVAgfCBQQ0lF X1JETEhfTElOS1VQKQo+ID4rI2RlZmluZSBQQ0lFX0wwU19FTlRSWSAgICAgICAgMHgxMQo+ID4r I2RlZmluZSBQQ0lFX0NMSUVOVF9HRU5FUkFMX0NPTlRST0wgICAweDAKPiA+KyNkZWZpbmUgUENJ RV9DTElFTlRfR0VORVJBTF9ERUJVRyAgICAgMHgxMDQKPiA+KyNkZWZpbmUgUENJRV9DTElFTlRf SE9UX1JFU0VUX0NUUkwgICAgICAweDE4MAo+ID4rI2RlZmluZSBQQ0lFX0NMSUVOVF9MVFNTTV9T VEFUVVMgICAgICAweDMwMAo+ID4rI2RlZmluZSBQQ0lFX0xUU1NNX0VOQUJMRV9FTkhBTkNFICAg ICAgIEJJVCg0KQo+ID4rI2RlZmluZSBQQ0lFX0xUU1NNX1NUQVRVU19NQVNLICAgICAgICBHRU5N QVNLKDUsIDApCj4gPisKPiA+K3N0cnVjdCByb2NrY2hpcF9wY2llIHsKPiA+KyAgICAgIHN0cnVj dCBkd19wY2llICBwY2k7Cj4gPisgICAgICB2b2lkIF9faW9tZW0gICAgKmFwYl9iYXNlOwo+ID4r ICAgICAgc3RydWN0IHBoeSAgICAgICpwaHk7Cj4gPisgICAgICBzdHJ1Y3QgY2xrX2J1bGtfZGF0 YSAgICAqY2xrczsKPiA+KyAgICAgIHVuc2lnbmVkIGludCAgICBjbGtfY250Owo+ID4rICAgICAg c3RydWN0IHJlc2V0X2NvbnRyb2wgICAgKnJzdDsKPiA+KyAgICAgIHN0cnVjdCBncGlvX2Rlc2Mg ICAgICAgICpyc3RfZ3BpbzsKPiA+KyAgICAgIHN0cnVjdCByZWd1bGF0b3IgICAgICAgICAgICAg ICAgKnZwY2llM3YzOwo+ID4rfTsKPiA+Kwo+ID4rc3RhdGljIGludCByb2NrY2hpcF9wY2llX3Jl YWRsX2FwYihzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAsCj4gPisgICAgICAgICAgIHUz MiByZWcpCj4gPit7Cj4gPisgICAgICByZXR1cm4gcmVhZGxfcmVsYXhlZChyb2NrY2hpcC0+YXBi X2Jhc2UgKyByZWcpOwo+ID4rfQo+ID4rCj4gPitzdGF0aWMgdm9pZCByb2NrY2hpcF9wY2llX3dy aXRlbF9hcGIoc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwLAo+ID4rICAgICAgdTMyIHZh bCwgdTMyIHJlZykKPiA+K3sKPiA+KyAgICAgIHdyaXRlbF9yZWxheGVkKHZhbCwgcm9ja2NoaXAt PmFwYl9iYXNlICsgcmVnKTsKPiA+K30KPiA+Kwo+ID4rc3RhdGljIHZvaWQgcm9ja2NoaXBfcGNp ZV9lbmFibGVfbHRzc20oc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwKQo+ID4rewo+ID4r ICAgICAgcm9ja2NoaXBfcGNpZV93cml0ZWxfYXBiKHJvY2tjaGlwLCBQQ0lFX0NMSUVOVF9FTkFC TEVfTFRTU00sCj4gPisgICAgICBQQ0lFX0NMSUVOVF9HRU5FUkFMX0NPTlRST0wpOwo+ID4rfQo+ ID4rCj4gPitzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfbGlua191cChzdHJ1Y3QgZHdfcGNpZSAq cGNpKQo+ID4rewo+ID4rICAgICAgc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwID0gdG9f cm9ja2NoaXBfcGNpZShwY2kpOwo+ID4rICAgICAgdTMyIHZhbCA9IHJvY2tjaGlwX3BjaWVfcmVh ZGxfYXBiKHJvY2tjaGlwLCBQQ0lFX0NMSUVOVF9MVFNTTV9TVEFUVVMpOwo+ID4rCj4gPisgICAg ICBpZiAoKHZhbCAmIFBDSUVfTElOS1VQKSA9PSBQQ0lFX0xJTktVUCAmJgo+ID4rICAgICAgICAg ICh2YWwgJiBQQ0lFX0xUU1NNX1NUQVRVU19NQVNLKSA9PSBQQ0lFX0wwU19FTlRSWSkKPiA+KyAg ICAgIHJldHVybiAxOwo+ID4rCj4gPisgICAgICByZXR1cm4gMDsKPiA+K30KPiA+Kwo+ID4rc3Rh dGljIGludCByb2NrY2hpcF9wY2llX3N0YXJ0X2xpbmsoc3RydWN0IGR3X3BjaWUgKnBjaSkKPiA+ K3sKPiA+KyAgICAgIHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2NrY2hpcCA9IHRvX3JvY2tjaGlw X3BjaWUocGNpKTsKPiA+Kwo+ID4rICAgICAgLyogUmVzZXQgZGV2aWNlICovCj4gPisgICAgICBn cGlvZF9zZXRfdmFsdWVfY2Fuc2xlZXAocm9ja2NoaXAtPnJzdF9ncGlvLCAwKTsKPiA+Kwo+ID4r ICAgICAgcm9ja2NoaXBfcGNpZV9lbmFibGVfbHRzc20ocm9ja2NoaXApOwo+ID4rCj4gPisgICAg ICAvKgo+ID4rICAgICAgKiBQQ0llIHJlcXVpcmVzIHRoZSByZWZjbGsgdG8gYmUgc3RhYmxlIGZv ciAxMDDCtXMgcHJpb3IgdG8gcmVsZWFzaW5nCj4gPisgICAgICAqIFBFUlNULiBTZWUgdGFibGUg Mi00IGluIHNlY3Rpb24gMi42LjIgQUMgU3BlY2lmaWNhdGlvbnMgb2YgdGhlIFBDSQo+ID4rICAg ICAgKiBFeHByZXNzIENhcmQgRWxlY3Ryb21lY2hhbmljYWwgU3BlY2lmaWNhdGlvbiwgMS4xLiBI b3dldmVyLCB3ZSBkb24ndAo+ID4rICAgICAgKiBrbm93IGlmIHRoZSByZWZjbGsgaXMgY29taW5n IGZyb20gUkMncyBQSFkgb3IgZXh0ZXJuYWwgT1NDLiBJZiBpdCdzCj4gPisgICAgICAqIGZyb20g UkMsIHNvIGVuYWJsaW5nIExUU1NNIGlzIHRoZSBqdXN0IHJpZ2h0IHBsYWNlIHRvIHJlbGVhc2Ug I1BFUlNULgo+ID4rICAgICAgKiBXZSBuZWVkIG1vcmUgZXh0cmEgdGltZSBhcyBiZWZvcmUsIHJh dGhlciB0aGFuIHNldHRpbmcganVzdAo+ID4rICAgICAgKiAxMDB1cyBhcyB3ZSBkb24ndCBrbm93 IGhvdyBsb25nIHNob3VsZCB0aGUgZGV2aWNlIG5lZWQgdG8gcmVzZXQuCj4gPisgICAgICAqLwo+ ID4rICAgICAgbXNsZWVwKDEwMCk7Cj4gPisgICAgICBncGlvZF9zZXRfdmFsdWVfY2Fuc2xlZXAo cm9ja2NoaXAtPnJzdF9ncGlvLCAxKTsKPiA+Kwo+ID4rICAgICAgcmV0dXJuIDA7Cj4gPit9Cj4g PisKPiA+K3N0YXRpYyBpbnQgcm9ja2NoaXBfcGNpZV9ob3N0X2luaXQoc3RydWN0IHBjaWVfcG9y dCAqcHApCj4gPit7Cj4gPisgICAgICBzdHJ1Y3QgZHdfcGNpZSAqcGNpID0gdG9fZHdfcGNpZV9m cm9tX3BwKHBwKTsKPiA+KyAgICAgIHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2NrY2hpcCA9IHRv X3JvY2tjaGlwX3BjaWUocGNpKTsKPiA+KyAgICAgIHUzMiB2YWwgPSBISVdPUkRfVVBEQVRFX0JJ VChQQ0lFX0xUU1NNX0VOQUJMRV9FTkhBTkNFKTsKPiA+Kwo+ID4rICAgICAgLyogTFRTU00gZW5h YmxlIGNvbnRyb2wgbW9kZSAqLwo+ID4rICAgICAgcm9ja2NoaXBfcGNpZV93cml0ZWxfYXBiKHJv Y2tjaGlwLCB2YWwsIFBDSUVfQ0xJRU5UX0hPVF9SRVNFVF9DVFJMKTsKPiA+Kwo+ID4rICAgICAg cm9ja2NoaXBfcGNpZV93cml0ZWxfYXBiKHJvY2tjaGlwLCBQQ0lFX0NMSUVOVF9SQ19NT0RFLAo+ ID4rICAgICAgUENJRV9DTElFTlRfR0VORVJBTF9DT05UUk9MKTsKPiA+Kwo+ID4rICAgICAgcmV0 dXJuIDA7Cj4gPit9Cj4gPisKPiA+K3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHdfcGNpZV9ob3N0X29w cyByb2NrY2hpcF9wY2llX2hvc3Rfb3BzID0gewo+ID4rICAgICAgLmhvc3RfaW5pdCA9IHJvY2tj aGlwX3BjaWVfaG9zdF9pbml0LAo+ID4rfTsKPiA+Kwo+ID4rc3RhdGljIGludCByb2NrY2hpcF9w Y2llX2Nsa19pbml0KHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2NrY2hpcCkKPiA+K3sKPiA+KyAg ICAgIHN0cnVjdCBkZXZpY2UgKmRldiA9IHJvY2tjaGlwLT5wY2kuZGV2Owo+ID4rICAgICAgaW50 IHJldDsKPiA+Kwo+ID4rICAgICAgcmV0ID0gZGV2bV9jbGtfYnVsa19nZXRfYWxsKGRldiwgJnJv Y2tjaGlwLT5jbGtzKTsKPiA+KyAgICAgIGlmIChyZXQgPCAwKQo+ID4rICAgICAgcmV0dXJuIHJl dDsKPiA+Kwo+ID4rICAgICAgcm9ja2NoaXAtPmNsa19jbnQgPSByZXQ7Cj4gPisKPiA+KyAgICAg IHJldHVybiBjbGtfYnVsa19wcmVwYXJlX2VuYWJsZShyb2NrY2hpcC0+Y2xrX2NudCwgcm9ja2No aXAtPmNsa3MpOwo+ID4rfQo+ID4rCj4gPitzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfcmVzb3Vy Y2VfZ2V0KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYsCj4gPisgICAgICAgICAgICBzdHJ1 Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXApCj4gPit7Cj4gPisgICAgICByb2NrY2hpcC0+YXBi X2Jhc2UgPSBkZXZtX3BsYXRmb3JtX2lvcmVtYXBfcmVzb3VyY2VfYnluYW1lKHBkZXYsICJhcGIi KTsKPiA+KyAgICAgIGlmIChJU19FUlIocm9ja2NoaXAtPmFwYl9iYXNlKSkKPiA+KyAgICAgIHJl dHVybiBQVFJfRVJSKHJvY2tjaGlwLT5hcGJfYmFzZSk7Cj4gPisKPiA+KyAgICAgIHJvY2tjaGlw LT5yc3RfZ3BpbyA9IGRldm1fZ3Bpb2RfZ2V0X29wdGlvbmFsKCZwZGV2LT5kZXYsICJyZXNldCIs Cj4gPisgICAgICAgICAgIEdQSU9EX09VVF9ISUdIKTsKPiA+KyAgICAgIGlmIChJU19FUlIocm9j a2NoaXAtPnJzdF9ncGlvKSkKPiA+KyAgICAgIHJldHVybiBQVFJfRVJSKHJvY2tjaGlwLT5yc3Rf Z3Bpbyk7Cj4gPisKPiA+KyAgICAgIHJldHVybiAwOwo+ID4rfQo+ID4rCj4gPitzdGF0aWMgaW50 IHJvY2tjaGlwX3BjaWVfcGh5X2luaXQoc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwKQo+ ID4rewo+ID4rICAgICAgc3RydWN0IGRldmljZSAqZGV2ID0gcm9ja2NoaXAtPnBjaS5kZXY7Cj4g PisgICAgICBpbnQgcmV0Owo+ID4rCj4gPisgICAgICByb2NrY2hpcC0+cGh5ID0gZGV2bV9waHlf Z2V0KGRldiwgInBjaWUtcGh5Iik7Cj4gPisgICAgICBpZiAoSVNfRVJSKHJvY2tjaGlwLT5waHkp KQo+ID4rICAgICAgcmV0dXJuIGRldl9lcnJfcHJvYmUoZGV2LCBQVFJfRVJSKHJvY2tjaGlwLT5w aHkpLAo+ID4rICAgICAgICAgICAibWlzc2luZyBQSFlcbiIpOwo+ID4rCj4gPisgICAgICByZXQg PSBwaHlfaW5pdChyb2NrY2hpcC0+cGh5KTsKPiA+KyAgICAgIGlmIChyZXQgPCAwKQo+ID4rICAg ICAgcmV0dXJuIHJldDsKPiA+Kwo+ID4rICAgICAgcmV0ID0gcGh5X3Bvd2VyX29uKHJvY2tjaGlw LT5waHkpOwo+ID4rICAgICAgaWYgKHJldCkKPiA+KyAgICAgIHBoeV9leGl0KHJvY2tjaGlwLT5w aHkpOwo+ID4rCj4gPisgICAgICByZXR1cm4gcmV0Owo+ID4rfQo+ID4rCj4gPitzdGF0aWMgdm9p ZCByb2NrY2hpcF9wY2llX3BoeV9kZWluaXQoc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlw KQo+ID4rewo+ID4rICAgICAgcGh5X2V4aXQocm9ja2NoaXAtPnBoeSk7Cj4gPisgICAgICBwaHlf cG93ZXJfb2ZmKHJvY2tjaGlwLT5waHkpOwo+ID4rfQo+ID4rCj4gPitzdGF0aWMgaW50IHJvY2tj aGlwX3BjaWVfcmVzZXRfY29udHJvbF9yZWxlYXNlKHN0cnVjdCByb2NrY2hpcF9wY2llICpyb2Nr Y2hpcCkKPiA+K3sKPiA+KyAgICAgIHN0cnVjdCBkZXZpY2UgKmRldiA9IHJvY2tjaGlwLT5wY2ku ZGV2Owo+ID4rCj4gPisgICAgICByb2NrY2hpcC0+cnN0ID0gZGV2bV9yZXNldF9jb250cm9sX2Fy cmF5X2dldF9leGNsdXNpdmUoZGV2KTsKPiA+KyAgICAgIGlmIChJU19FUlIocm9ja2NoaXAtPnJz dCkpCj4gPisgICAgICByZXR1cm4gZGV2X2Vycl9wcm9iZShkZXYsIFBUUl9FUlIocm9ja2NoaXAt PnJzdCksCj4gPisgICAgICAgICAgICJmYWlsZWQgdG8gZ2V0IHJlc2V0IGxpbmVzXG4iKTsKPiA+ Kwo+ID4rICAgICAgcmV0dXJuIHJlc2V0X2NvbnRyb2xfZGVhc3NlcnQocm9ja2NoaXAtPnJzdCk7 Cj4gPit9Cj4gPisKPiA+K3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHdfcGNpZV9vcHMgZHdfcGNpZV9v cHMgPSB7Cj4gPisgICAgICAubGlua191cCA9IHJvY2tjaGlwX3BjaWVfbGlua191cCwKPiA+KyAg ICAgIC5zdGFydF9saW5rID0gcm9ja2NoaXBfcGNpZV9zdGFydF9saW5rLAo+ID4rfTsKPiA+Kwo+ ID4rc3RhdGljIGludCByb2NrY2hpcF9wY2llX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2Ug KnBkZXYpCj4gPit7Cj4gPisgICAgICBzdHJ1Y3QgZGV2aWNlICpkZXYgPSAmcGRldi0+ZGV2Owo+ ID4rICAgICAgc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwOwo+ID4rICAgICAgc3RydWN0 IHBjaWVfcG9ydCAqcHA7Cj4gPisgICAgICBpbnQgcmV0Owo+ID4rCj4gPisgICAgICByb2NrY2hp cCA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZigqcm9ja2NoaXApLCBHRlBfS0VSTkVMKTsKPiA+ KyAgICAgIGlmICghcm9ja2NoaXApCj4gPisgICAgICByZXR1cm4gLUVOT01FTTsKPiA+Kwo+ID4r ICAgICAgcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgcm9ja2NoaXApOwo+ID4rCj4gPisgICAg ICByb2NrY2hpcC0+cGNpLmRldiA9IGRldjsKPiA+KyAgICAgIHJvY2tjaGlwLT5wY2kub3BzID0g JmR3X3BjaWVfb3BzOwo+ID4rCj4gPisgICAgICBwcCA9ICZyb2NrY2hpcC0+cGNpLnBwOwo+ID4r ICAgICAgcHAtPm9wcyA9ICZyb2NrY2hpcF9wY2llX2hvc3Rfb3BzOwo+ID4rCj4gPisgICAgICBy ZXQgPSByb2NrY2hpcF9wY2llX3Jlc291cmNlX2dldChwZGV2LCByb2NrY2hpcCk7Cj4gPisgICAg ICBpZiAocmV0KQo+ID4rICAgICAgcmV0dXJuIHJldDsKPiA+Kwo+ID4rICAgICAgLyogRE9OJ1Qg TU9WRSBNRTogbXVzdCBiZSBlbmFibGUgYmVmb3JlIFBIWSBpbml0ICovCj4gPisgICAgICByb2Nr Y2hpcC0+dnBjaWUzdjMgPSBkZXZtX3JlZ3VsYXRvcl9nZXRfb3B0aW9uYWwoZGV2LCAidnBjaWUz djMiKTsKPiA+KyAgICAgIGlmIChJU19FUlIocm9ja2NoaXAtPnZwY2llM3YzKSkKPiA+KyAgICAg IGlmIChQVFJfRVJSKHJvY2tjaGlwLT52cGNpZTN2MykgIT0gLUVOT0RFVikKPiA+KyAgICAgIHJl dHVybiBkZXZfZXJyX3Byb2JlKGRldiwgUFRSX0VSUihyb2NrY2hpcC0+dnBjaWUzdjMpLAo+ID4r ICAgICAgImZhaWxlZCB0byBnZXQgdnBjaWUzdjMgcmVndWxhdG9yXG4iKTsKPiA+Kwo+ID4rICAg ICAgcmV0ID0gcmVndWxhdG9yX2VuYWJsZShyb2NrY2hpcC0+dnBjaWUzdjMpOwo+ID4rICAgICAg aWYgKHJldCkgewo+ID4rICAgICAgZGV2X2VycihkZXYsICJmYWlsZWQgdG8gZW5hYmxlIHZwY2ll M3YzIHJlZ3VsYXRvclxuIik7Cj4gPisgICAgICByZXR1cm4gcmV0Owo+ID4rICAgICAgfQo+ID4r Cj4gPisgICAgICByZXQgPSByb2NrY2hpcF9wY2llX3BoeV9pbml0KHJvY2tjaGlwKTsKPiA+KyAg ICAgIGlmIChyZXQpCj4gPisgICAgICBnb3RvIGRpc2FibGVfcmVndWxhdG9yOwo+ID4rCj4gPisg ICAgICByZXQgPSByb2NrY2hpcF9wY2llX3Jlc2V0X2NvbnRyb2xfcmVsZWFzZShyb2NrY2hpcCk7 Cj4gPisgICAgICBpZiAocmV0KQo+ID4rICAgICAgZ290byBkZWluaXRfcGh5Owo+ID4rCj4gPisg ICAgICByZXQgPSByb2NrY2hpcF9wY2llX2Nsa19pbml0KHJvY2tjaGlwKTsKPiA+KyAgICAgIGlm IChyZXQpCj4gPisgICAgICBnb3RvIGRlaW5pdF9waHk7Cj4gPisKPiA+KyAgICAgIHJldCA9IGR3 X3BjaWVfaG9zdF9pbml0KHBwKTsKPiA+KyAgICAgIGlmICghcmV0KQo+ID4rICAgICAgcmV0dXJu IDA7Cj4gPisKPiA+KyAgICAgIGNsa19idWxrX2Rpc2FibGVfdW5wcmVwYXJlKHJvY2tjaGlwLT5j bGtfY250LCByb2NrY2hpcC0+Y2xrcyk7Cj4gPitkZWluaXRfcGh5Ogo+ID4rICAgICAgcm9ja2No aXBfcGNpZV9waHlfZGVpbml0KHJvY2tjaGlwKTsKPiA+K2Rpc2FibGVfcmVndWxhdG9yOgo+ID4r ICAgICAgcmVndWxhdG9yX2Rpc2FibGUocm9ja2NoaXAtPnZwY2llM3YzKTsKPiA+Kwo+ID4rICAg ICAgcmV0dXJuIHJldDsKPiA+K30KPiA+Kwo+ID4rc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZp Y2VfaWQgcm9ja2NoaXBfcGNpZV9vZl9tYXRjaFtdID0gewo+ID4rICAgICAgeyAuY29tcGF0aWJs ZSA9ICJyb2NrY2hpcCxyazM1NjgtcGNpZSIsIH0sCj4gPisgICAgICB7fSwKPiA+K307Cj4gPisK PiA+K3N0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIHJvY2tjaGlwX3BjaWVfZHJpdmVyID0g ewo+ID4rICAgICAgLmRyaXZlciA9IHsKPiA+KyAgICAgIC5uYW1lICAgPSAicm9ja2NoaXAtZHct cGNpZSIsCj4gPisgICAgICAub2ZfbWF0Y2hfdGFibGUgPSByb2NrY2hpcF9wY2llX29mX21hdGNo LAo+ID4rICAgICAgLnN1cHByZXNzX2JpbmRfYXR0cnMgPSB0cnVlLAo+ID4rICAgICAgfSwKPiA+ KyAgICAgIC5wcm9iZSA9IHJvY2tjaGlwX3BjaWVfcHJvYmUsCj4gPit9Owo+ID4rYnVpbHRpbl9w bGF0Zm9ybV9kcml2ZXIocm9ja2NoaXBfcGNpZV9kcml2ZXIpOwo+ID4tLQo+ID4yLjI1LjEKPiA+ Cj4gPgo+ID4KPiA+CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpMaW51eC1yb2NrY2hpcCBtYWlsaW5nIGxpc3QKTGludXgtcm9ja2NoaXBAbGlzdHMuaW5m cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp bnV4LXJvY2tjaGlwCg==