From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D69AC433ED for ; Wed, 28 Apr 2021 16:20:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0D08613E1 for ; Wed, 28 Apr 2021 16:20:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240349AbhD1QVO (ORCPT ); Wed, 28 Apr 2021 12:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239947AbhD1QVO (ORCPT ); Wed, 28 Apr 2021 12:21:14 -0400 Received: from mail-yb1-xb33.google.com (mail-yb1-xb33.google.com [IPv6:2607:f8b0:4864:20::b33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8E9C061573; Wed, 28 Apr 2021 09:20:27 -0700 (PDT) Received: by mail-yb1-xb33.google.com with SMTP id p202so30975609ybg.8; Wed, 28 Apr 2021 09:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=sZLMmEQlltT0b2hnZFwUuOLpdjUHwWYcsq0zsCZ8p6s=; b=BRXQc3J6ju+mldxyR03odqbzaI5DEUtbtSxGH7K6xL4VkTauL90AxhwSh+mfq+0SJX +FXavJntHJZRj2EjYBuB1GSPSrELjE3Kz31m+wFteJM546KSK5HIxt8jNtAUmFX1dbay KxVwURXOqCIZhgvyDilqKe74WWpmbfCRwIKQftNLj0oyGxU36E0R08xeWTMkrfDxZ9tn 65xEojo+QF6zoCnGrdEfH6cmQSE1vsK9+5VcuUUG5bZBzGuBiAJ7txjzy+XXygFemmrr VVDX0L5Ewq25nicbIFvICJgW+EOMSR04VGHY2/LvvYl4ZJthzXNtWGoobujJC6UcZ+k5 uYLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=sZLMmEQlltT0b2hnZFwUuOLpdjUHwWYcsq0zsCZ8p6s=; b=TIFQFnYUOAfsoQ8u/u6b19FzkIUQzMBSXAamJzvjFMRsMXIzBwpSQlKGEsCh5nxXBz 23pezo2tNmOQlvXDfuAFa4yOYxAGQtdgf9wsuqDEHpL6ktnn4aX8Bb3iOkszfvEwII/B fEeNWH896G/vBRgmq7d5ndwpv9uiaIX9252COvv7HvoOvFmwYqoLB4jiICs6qB4gpMpU SqL+r7kruyD+u0HvKHweZwSNrj40UdtZIE5tpNlhLr1lhcYIzfVgIVO3lIH20PvJI4gl IhWH11sFkjdpAuIuxg9ZeHWsQaKy51YswPgaV11MWT2oTzLvLtYQSPEPmYDvLP4jEnJn EoPA== X-Gm-Message-State: AOAM532L9tXtwk5Kf4cd3BexFyJ55aPgrsDZw4rjh5zZreDq2JBZv66q 2ScClPWT4/uOC2/XZ2uUjC8mjGxE/Tch+6f3djU= X-Google-Smtp-Source: ABdhPJxDV69UmsKnp/NK5E0KYeHkxvAI0wY5a4CTshKqJUhC5aoX74tHEx5LipbbzX8VeTcqO/coeB9MSIh94vtj2so= X-Received: by 2002:a5b:303:: with SMTP id j3mr38799743ybp.433.1619626827016; Wed, 28 Apr 2021 09:20:27 -0700 (PDT) MIME-Version: 1.0 References: <20210414070325.924789-1-xxm@rock-chips.com> In-Reply-To: <20210414070325.924789-1-xxm@rock-chips.com> From: Peter Geis Date: Wed, 28 Apr 2021 12:20:15 -0400 Message-ID: Subject: Re: [PATCH v7] PCI: rockchip: Add Rockchip RK356X host controller driver To: Simon Xue Cc: Bjorn Helgaas , Lorenzo Pieralisi , linux-pci@vger.kernel.org, "open list:ARM/Rockchip SoC..." , devicetree@vger.kernel.org, Rob Herring , Johan Jonker , Heiko Stuebner , Shawn Lin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Apr 14, 2021 at 3:05 AM Simon Xue wrote: > > Add a driver for the DesignWare-based PCIe controller found on > RK356X. The existing pcie-rockchip-host driver is only used for > the Rockchip-designed IP found on RK3399. Good Afternoon, I've encountered a bit of an issue with this driver. Unfortunately it does not support legacy interrupts, meaning any PCIe device that doesn't support MSIs will fail to enumerate: [ 14.932078] pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=3D-2= 2 [ 14.932708] snd_hda_intel 0000:01:00.1: assign IRQ: got 0 [ 14.933687] snd_hda_intel 0000:01:00.1: enabling device (0000 -> 0002) [ 14.934317] snd_hda_intel 0000:01:00.1: Disabling MSI [ 14.934783] snd_hda_intel 0000:01:00.1: Force to snoop mode by module op= tion [ 14.935534] snd_hda_intel 0000:01:00.1: enabling bus mastering [ 14.939764] snd_hda_intel 0000:01:00.1: unable to grab IRQ 0, disabling device Are there plans to support legacy interrupts with the rk3568 controllers? Thanks, Peter Geis > > Signed-off-by: Simon Xue > Signed-off-by: Shawn Lin > --- > drivers/pci/controller/dwc/Kconfig | 10 + > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 277 ++++++++++++++++++ > 3 files changed, 288 insertions(+) > create mode 100644 drivers/pci/controller/dwc/pcie-dw-rockchip.c > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/= dwc/Kconfig > index 423d35872ce4..8ab027ba8c04 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -214,6 +214,16 @@ config PCIE_ARTPEC6_EP > Enables support for the PCIe controller in the ARTPEC-6 SoC to = work in > endpoint mode. This uses the DesignWare core. > > +config PCIE_ROCKCHIP_DW_HOST > + bool "Rockchip DesignWare PCIe controller" > + select PCIE_DW > + select PCIE_DW_HOST > + depends on ARCH_ROCKCHIP || COMPILE_TEST > + depends on OF > + help > + Enables support for the DesignWare PCIe controller in the > + Rockchip SoC except RK3399. > + > config PCIE_INTEL_GW > bool "Intel Gateway PCIe host controller support" > depends on OF && (X86 || COMPILE_TEST) > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller= /dwc/Makefile > index 952d01941f23..0104659dfe88 100644 > --- a/drivers/pci/controller/dwc/Makefile > +++ b/drivers/pci/controller/dwc/Makefile > @@ -14,6 +14,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) +=3D pci-layerscape-ep.= o > obj-$(CONFIG_PCIE_QCOM) +=3D pcie-qcom.o > obj-$(CONFIG_PCIE_ARMADA_8K) +=3D pcie-armada8k.o > obj-$(CONFIG_PCIE_ARTPEC6) +=3D pcie-artpec6.o > +obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) +=3D pcie-dw-rockchip.o > obj-$(CONFIG_PCIE_INTEL_GW) +=3D pcie-intel-gw.o > obj-$(CONFIG_PCIE_KIRIN) +=3D pcie-kirin.o > obj-$(CONFIG_PCIE_HISI_STB) +=3D pcie-histb.o > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/= controller/dwc/pcie-dw-rockchip.c > new file mode 100644 > index 000000000000..3f060144eeab > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -0,0 +1,277 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PCIe host controller driver for Rockchip SoCs. > + * > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. > + * http://www.rock-chips.com > + * > + * Author: Simon Xue > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "pcie-designware.h" > + > +/* > + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write > + * mask for the lower 16 bits. > + */ > +#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) > +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) > + > +#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) > + > +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > +#define PCIE_SMLH_LINKUP BIT(16) > +#define PCIE_RDLH_LINKUP BIT(17) > +#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LIN= KUP) > +#define PCIE_L0S_ENTRY 0x11 > +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > +#define PCIE_CLIENT_GENERAL_DEBUG 0x104 > +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 > +#define PCIE_CLIENT_LTSSM_STATUS 0x300 > +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > + > +struct rockchip_pcie { > + struct dw_pcie pci; > + void __iomem *apb_base; > + struct phy *phy; > + struct clk_bulk_data *clks; > + unsigned int clk_cnt; > + struct reset_control *rst; > + struct gpio_desc *rst_gpio; > + struct regulator *vpcie3v3; > +}; > + > +static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, > + u32 reg) > +{ > + return readl(rockchip->apb_base + reg); > +} > + > +static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, > + u32 val, u32 reg) > +{ > + writel(val, rockchip->apb_base + reg); > +} > + > +static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) > +{ > + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, > + PCIE_CLIENT_GENERAL_CONTROL); > +} > + > +static int rockchip_pcie_link_up(struct dw_pcie *pci) > +{ > + struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > + u32 val =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_S= TATUS); > + > + if ((val & (PCIE_RDLH_LINKUP | PCIE_SMLH_LINKUP)) =3D=3D PCIE_LIN= KUP && > + (val & GENMASK(5, 0)) =3D=3D PCIE_L0S_ENTRY) > + return 1; > + > + return 0; > +} > + > +static int rockchip_pcie_start_link(struct dw_pcie *pci) > +{ > + struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > + > + /* Reset device */ > + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); > + > + rockchip_pcie_enable_ltssm(rockchip); > + > + /* > + * PCIe requires the refclk to be stable for 100=C2=B5s prior to = releasing > + * PERST. See table 2-4 in section 2.6.2 AC Specifications of the= PCI > + * Express Card Electromechanical Specification, 1.1. However, we= don't > + * know if the refclk is coming from RC's PHY or external OSC. If= it's > + * from RC, so enabling LTSSM is the just right place to release = #PERST. > + * We need more extra time as before, rather than setting just > + * 100us as we don't know how long should the device need to rese= t. > + */ > + msleep(100); > + gpiod_set_value_cansleep(rockchip->rst_gpio, 1); > + > + return 0; > +} > + > +static int rockchip_pcie_host_init(struct pcie_port *pp) > +{ > + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); > + struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > + u32 val; > + > + /* LTSSM enable control mode */ > + val =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_C= TRL); > + val |=3D PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE <= < 16); > + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTR= L); > + > + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, > + PCIE_CLIENT_GENERAL_CONTROL); > + > + return 0; > +} > + > +static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { > + .host_init =3D rockchip_pcie_host_init, > +}; > + > +static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) > +{ > + struct device *dev =3D rockchip->pci.dev; > + int ret; > + > + ret =3D devm_clk_bulk_get_all(dev, &rockchip->clks); > + if (ret < 0) > + return ret; > + > + rockchip->clk_cnt =3D ret; > + > + return clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks)= ; > +} > + > +static int rockchip_pcie_resource_get(struct platform_device *pdev, > + struct rockchip_pcie *rockchip) > +{ > + rockchip->apb_base =3D devm_platform_ioremap_resource_byname(pdev= , "apb"); > + if (IS_ERR(rockchip->apb_base)) > + return PTR_ERR(rockchip->apb_base); > + > + rockchip->rst_gpio =3D devm_gpiod_get_optional(&pdev->dev, "reset= ", > + GPIOD_OUT_HIGH); > + if (IS_ERR(rockchip->rst_gpio)) > + return PTR_ERR(rockchip->rst_gpio); > + > + return 0; > +} > + > +static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip) > +{ > + struct device *dev =3D rockchip->pci.dev; > + int ret; > + > + rockchip->phy =3D devm_phy_get(dev, "pcie-phy"); > + if (IS_ERR(rockchip->phy)) > + return dev_err_probe(dev, PTR_ERR(rockchip->phy), > + "missing PHY\n"); > + > + ret =3D phy_init(rockchip->phy); > + if (ret < 0) > + return ret; > + > + ret =3D phy_power_on(rockchip->phy); > + if (ret) > + phy_exit(rockchip->phy); > + > + return ret; > +} > + > +static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) > +{ > + phy_exit(rockchip->phy); > + phy_power_off(rockchip->phy); > +} > + > +static int rockchip_pcie_reset_control_release(struct rockchip_pcie *roc= kchip) > +{ > + struct device *dev =3D rockchip->pci.dev; > + > + rockchip->rst =3D devm_reset_control_array_get_exclusive(dev); > + if (IS_ERR(rockchip->rst)) > + return dev_err_probe(dev, PTR_ERR(rockchip->rst), > + "failed to get reset lines\n"); > + > + return reset_control_deassert(rockchip->rst); > +} > + > +static const struct dw_pcie_ops dw_pcie_ops =3D { > + .link_up =3D rockchip_pcie_link_up, > + .start_link =3D rockchip_pcie_start_link, > +}; > + > +static int rockchip_pcie_probe(struct platform_device *pdev) > +{ > + struct device *dev =3D &pdev->dev; > + struct rockchip_pcie *rockchip; > + struct pcie_port *pp; > + int ret; > + > + rockchip =3D devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); > + if (!rockchip) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, rockchip); > + > + rockchip->pci.dev =3D dev; > + rockchip->pci.ops =3D &dw_pcie_ops; > + > + pp =3D &rockchip->pci.pp; > + pp->ops =3D &rockchip_pcie_host_ops; > + > + ret =3D rockchip_pcie_resource_get(pdev, rockchip); > + if (ret) > + return ret; > + > + /* DON'T MOVE ME: must be enable before PHY init */ > + rockchip->vpcie3v3 =3D devm_regulator_get_optional(dev, "vpcie3v3= "); > + if (IS_ERR(rockchip->vpcie3v3)) > + if (PTR_ERR(rockchip->vpcie3v3) !=3D -ENODEV) > + return dev_err_probe(dev, PTR_ERR(rockchip->vpcie= 3v3), > + "failed to get vpcie3v3 regulator= \n"); > + > + ret =3D regulator_enable(rockchip->vpcie3v3); > + if (ret) { > + dev_err(dev, "failed to enable vpcie3v3 regulator\n"); > + return ret; > + } > + > + ret =3D rockchip_pcie_phy_init(rockchip); > + if (ret) > + goto disable_regulator; > + > + ret =3D rockchip_pcie_reset_control_release(rockchip); > + if (ret) > + goto deinit_phy; > + > + ret =3D rockchip_pcie_clk_init(rockchip); > + if (ret) > + goto deinit_phy; > + > + ret =3D dw_pcie_host_init(pp); > + if (!ret) > + return 0; > + > + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); > +deinit_phy: > + rockchip_pcie_phy_deinit(rockchip); > +disable_regulator: > + regulator_disable(rockchip->vpcie3v3); > + > + return ret; > +} > + > +static const struct of_device_id rockchip_pcie_of_match[] =3D { > + { .compatible =3D "rockchip,rk3568-pcie", }, > + {}, > +}; > + > +static struct platform_driver rockchip_pcie_driver =3D { > + .driver =3D { > + .name =3D "rockchip-dw-pcie", > + .of_match_table =3D rockchip_pcie_of_match, > + .suppress_bind_attrs =3D true, > + }, > + .probe =3D rockchip_pcie_probe, > +}; > +builtin_platform_driver(rockchip_pcie_driver); > -- > 2.25.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E91FC433B4 for ; Wed, 28 Apr 2021 16:20:43 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) 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sfid-20210428_092029_912708_8735C446 X-CRM114-Status: GOOD ( 37.40 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org T24gV2VkLCBBcHIgMTQsIDIwMjEgYXQgMzowNSBBTSBTaW1vbiBYdWUgPHh4bUByb2NrLWNoaXBz LmNvbT4gd3JvdGU6Cj4KPiBBZGQgYSBkcml2ZXIgZm9yIHRoZSBEZXNpZ25XYXJlLWJhc2VkIFBD SWUgY29udHJvbGxlciBmb3VuZCBvbgo+IFJLMzU2WC4gVGhlIGV4aXN0aW5nIHBjaWUtcm9ja2No aXAtaG9zdCBkcml2ZXIgaXMgb25seSB1c2VkIGZvcgo+IHRoZSBSb2NrY2hpcC1kZXNpZ25lZCBJ UCBmb3VuZCBvbiBSSzMzOTkuCgpHb29kIEFmdGVybm9vbiwKCkkndmUgZW5jb3VudGVyZWQgYSBi aXQgb2YgYW4gaXNzdWUgd2l0aCB0aGlzIGRyaXZlci4KVW5mb3J0dW5hdGVseSBpdCBkb2VzIG5v dCBzdXBwb3J0IGxlZ2FjeSBpbnRlcnJ1cHRzLCBtZWFuaW5nIGFueSBQQ0llCmRldmljZSB0aGF0 IGRvZXNuJ3Qgc3VwcG9ydCBNU0lzIHdpbGwgZmFpbCB0byBlbnVtZXJhdGU6ClsgICAxNC45MzIw NzhdIHBjaWVwb3J0IDAwMDA6MDA6MDAuMDogb2ZfaXJxX3BhcnNlX3BjaTogZmFpbGVkIHdpdGgg cmM9LTIyClsgICAxNC45MzI3MDhdIHNuZF9oZGFfaW50ZWwgMDAwMDowMTowMC4xOiBhc3NpZ24g SVJROiBnb3QgMApbICAgMTQuOTMzNjg3XSBzbmRfaGRhX2ludGVsIDAwMDA6MDE6MDAuMTogZW5h YmxpbmcgZGV2aWNlICgwMDAwIC0+IDAwMDIpClsgICAxNC45MzQzMTddIHNuZF9oZGFfaW50ZWwg MDAwMDowMTowMC4xOiBEaXNhYmxpbmcgTVNJClsgICAxNC45MzQ3ODNdIHNuZF9oZGFfaW50ZWwg MDAwMDowMTowMC4xOiBGb3JjZSB0byBzbm9vcCBtb2RlIGJ5IG1vZHVsZSBvcHRpb24KWyAgIDE0 LjkzNTUzNF0gc25kX2hkYV9pbnRlbCAwMDAwOjAxOjAwLjE6IGVuYWJsaW5nIGJ1cyBtYXN0ZXJp bmcKWyAgIDE0LjkzOTc2NF0gc25kX2hkYV9pbnRlbCAwMDAwOjAxOjAwLjE6IHVuYWJsZSB0byBn cmFiIElSUSAwLApkaXNhYmxpbmcgZGV2aWNlCgpBcmUgdGhlcmUgcGxhbnMgdG8gc3VwcG9ydCBs ZWdhY3kgaW50ZXJydXB0cyB3aXRoIHRoZSByazM1NjggY29udHJvbGxlcnM/CgpUaGFua3MsClBl dGVyIEdlaXMKCj4KPiBTaWduZWQtb2ZmLWJ5OiBTaW1vbiBYdWUgPHh4bUByb2NrLWNoaXBzLmNv bT4KPiBTaWduZWQtb2ZmLWJ5OiBTaGF3biBMaW4gPHNoYXduLmxpbkByb2NrLWNoaXBzLmNvbT4K PiAtLS0KPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvS2NvbmZpZyAgICAgICAgICAgIHwg IDEwICsKPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvTWFrZWZpbGUgICAgICAgICAgIHwg ICAxICsKPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kdy1yb2NrY2hpcC5jIHwg Mjc3ICsrKysrKysrKysrKysrKysrKwo+ICAzIGZpbGVzIGNoYW5nZWQsIDI4OCBpbnNlcnRpb25z KCspCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2ll LWR3LXJvY2tjaGlwLmMKPgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3 Yy9LY29uZmlnIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvS2NvbmZpZwo+IGluZGV4IDQy M2QzNTg3MmNlNC4uOGFiMDI3YmE4YzA0IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRy b2xsZXIvZHdjL0tjb25maWcKPiArKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9LY29u ZmlnCj4gQEAgLTIxNCw2ICsyMTQsMTYgQEAgY29uZmlnIFBDSUVfQVJUUEVDNl9FUAo+ICAgICAg ICAgICBFbmFibGVzIHN1cHBvcnQgZm9yIHRoZSBQQ0llIGNvbnRyb2xsZXIgaW4gdGhlIEFSVFBF Qy02IFNvQyB0byB3b3JrIGluCj4gICAgICAgICAgIGVuZHBvaW50IG1vZGUuIFRoaXMgdXNlcyB0 aGUgRGVzaWduV2FyZSBjb3JlLgo+Cj4gK2NvbmZpZyBQQ0lFX1JPQ0tDSElQX0RXX0hPU1QKPiAr ICAgICAgIGJvb2wgIlJvY2tjaGlwIERlc2lnbldhcmUgUENJZSBjb250cm9sbGVyIgo+ICsgICAg ICAgc2VsZWN0IFBDSUVfRFcKPiArICAgICAgIHNlbGVjdCBQQ0lFX0RXX0hPU1QKPiArICAgICAg IGRlcGVuZHMgb24gQVJDSF9ST0NLQ0hJUCB8fCBDT01QSUxFX1RFU1QKPiArICAgICAgIGRlcGVu ZHMgb24gT0YKPiArICAgICAgIGhlbHAKPiArICAgICAgICAgRW5hYmxlcyBzdXBwb3J0IGZvciB0 aGUgRGVzaWduV2FyZSBQQ0llIGNvbnRyb2xsZXIgaW4gdGhlCj4gKyAgICAgICAgIFJvY2tjaGlw IFNvQyBleGNlcHQgUkszMzk5Lgo+ICsKPiAgY29uZmlnIFBDSUVfSU5URUxfR1cKPiAgICAgICAg IGJvb2wgIkludGVsIEdhdGV3YXkgUENJZSBob3N0IGNvbnRyb2xsZXIgc3VwcG9ydCIKPiAgICAg ICAgIGRlcGVuZHMgb24gT0YgJiYgKFg4NiB8fCBDT01QSUxFX1RFU1QpCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL01ha2VmaWxlIGIvZHJpdmVycy9wY2kvY29udHJv bGxlci9kd2MvTWFrZWZpbGUKPiBpbmRleCA5NTJkMDE5NDFmMjMuLjAxMDQ2NTlkZmU4OCAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9NYWtlZmlsZQo+ICsrKyBiL2Ry aXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL01ha2VmaWxlCj4gQEAgLTE0LDYgKzE0LDcgQEAgb2Jq LSQoQ09ORklHX1BDSV9MQVlFUlNDQVBFX0VQKSArPSBwY2ktbGF5ZXJzY2FwZS1lcC5vCj4gIG9i ai0kKENPTkZJR19QQ0lFX1FDT00pICs9IHBjaWUtcWNvbS5vCj4gIG9iai0kKENPTkZJR19QQ0lF X0FSTUFEQV84SykgKz0gcGNpZS1hcm1hZGE4ay5vCj4gIG9iai0kKENPTkZJR19QQ0lFX0FSVFBF QzYpICs9IHBjaWUtYXJ0cGVjNi5vCj4gK29iai0kKENPTkZJR19QQ0lFX1JPQ0tDSElQX0RXX0hP U1QpICs9IHBjaWUtZHctcm9ja2NoaXAubwo+ICBvYmotJChDT05GSUdfUENJRV9JTlRFTF9HVykg Kz0gcGNpZS1pbnRlbC1ndy5vCj4gIG9iai0kKENPTkZJR19QQ0lFX0tJUklOKSArPSBwY2llLWtp cmluLm8KPiAgb2JqLSQoQ09ORklHX1BDSUVfSElTSV9TVEIpICs9IHBjaWUtaGlzdGIubwo+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWR3LXJvY2tjaGlwLmMg Yi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWR3LXJvY2tjaGlwLmMKPiBuZXcgZmls ZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAwMDAwMC4uM2YwNjAxNDRlZWFiCj4gLS0tIC9k ZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZHctcm9ja2No aXAuYwo+IEBAIC0wLDAgKzEsMjc3IEBACj4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBH UEwtMi4wCj4gKy8qCj4gKyAqIFBDSWUgaG9zdCBjb250cm9sbGVyIGRyaXZlciBmb3IgUm9ja2No aXAgU29Dcy4KPiArICoKPiArICogQ29weXJpZ2h0IChDKSAyMDIxIFJvY2tjaGlwIEVsZWN0cm9u aWNzIENvLiwgTHRkLgo+ICsgKiAgICAgICAgICAgICBodHRwOi8vd3d3LnJvY2stY2hpcHMuY29t Cj4gKyAqCj4gKyAqIEF1dGhvcjogU2ltb24gWHVlIDx4eG1Acm9jay1jaGlwcy5jb20+Cj4gKyAq Lwo+ICsKPiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgo+ICsjaW5jbHVkZSA8bGludXgvZ3Bpby9j b25zdW1lci5oPgo+ICsjaW5jbHVkZSA8bGludXgvbWZkL3N5c2Nvbi5oPgo+ICsjaW5jbHVkZSA8 bGludXgvbW9kdWxlLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4KPiArI2luY2x1 ZGUgPGxpbnV4L3BoeS9waHkuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5o Pgo+ICsjaW5jbHVkZSA8bGludXgvcmVnbWFwLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9yZXNldC5o Pgo+ICsKPiArI2luY2x1ZGUgInBjaWUtZGVzaWdud2FyZS5oIgo+ICsKPiArLyoKPiArICogVGhl IHVwcGVyIDE2IGJpdHMgb2YgUENJRV9DTElFTlRfQ09ORklHIGFyZSBhIHdyaXRlCj4gKyAqIG1h c2sgZm9yIHRoZSBsb3dlciAxNiBiaXRzLgo+ICsgKi8KPiArI2RlZmluZSBISVdPUkRfVVBEQVRF KG1hc2ssIHZhbCkgKCgobWFzaykgPDwgMTYpIHwgKHZhbCkpCj4gKyNkZWZpbmUgSElXT1JEX1VQ REFURV9CSVQodmFsKSBISVdPUkRfVVBEQVRFKHZhbCwgdmFsKQo+ICsKPiArI2RlZmluZSB0b19y b2NrY2hpcF9wY2llKHgpIGRldl9nZXRfZHJ2ZGF0YSgoeCktPmRldikKPiArCj4gKyNkZWZpbmUg UENJRV9DTElFTlRfUkNfTU9ERSAgICAgICAgICAgIEhJV09SRF9VUERBVEVfQklUKDB4NDApCj4g KyNkZWZpbmUgUENJRV9DTElFTlRfRU5BQkxFX0xUU1NNICAgICAgIEhJV09SRF9VUERBVEVfQklU KDB4YykKPiArI2RlZmluZSBQQ0lFX1NNTEhfTElOS1VQICAgICAgICAgICAgICAgQklUKDE2KQo+ ICsjZGVmaW5lIFBDSUVfUkRMSF9MSU5LVVAgICAgICAgICAgICAgICBCSVQoMTcpCj4gKyNkZWZp bmUgUENJRV9MSU5LVVAgICAgICAgICAgICAgICAgICAgIChQQ0lFX1NNTEhfTElOS1VQIHwgUENJ RV9SRExIX0xJTktVUCkKPiArI2RlZmluZSBQQ0lFX0wwU19FTlRSWSAgICAgICAgICAgICAgICAg MHgxMQo+ICsjZGVmaW5lIFBDSUVfQ0xJRU5UX0dFTkVSQUxfQ09OVFJPTCAgICAweDAKPiArI2Rl ZmluZSBQQ0lFX0NMSUVOVF9HRU5FUkFMX0RFQlVHICAgICAgMHgxMDQKPiArI2RlZmluZSBQQ0lF X0NMSUVOVF9IT1RfUkVTRVRfQ1RSTCAgICAgIDB4MTgwCj4gKyNkZWZpbmUgUENJRV9DTElFTlRf TFRTU01fU1RBVFVTICAgICAgIDB4MzAwCj4gKyNkZWZpbmUgUENJRV9MVFNTTV9FTkFCTEVfRU5I QU5DRSAgICAgICBCSVQoNCkKPiArCj4gK3N0cnVjdCByb2NrY2hpcF9wY2llIHsKPiArICAgICAg IHN0cnVjdCBkd19wY2llICAgICAgICAgICAgICAgICAgcGNpOwo+ICsgICAgICAgdm9pZCBfX2lv bWVtICAgICAgICAgICAgICAgICAgICAqYXBiX2Jhc2U7Cj4gKyAgICAgICBzdHJ1Y3QgcGh5ICAg ICAgICAgICAgICAgICAgICAgICpwaHk7Cj4gKyAgICAgICBzdHJ1Y3QgY2xrX2J1bGtfZGF0YSAg ICAgICAgICAgICpjbGtzOwo+ICsgICAgICAgdW5zaWduZWQgaW50ICAgICAgICAgICAgICAgICAg ICBjbGtfY250Owo+ICsgICAgICAgc3RydWN0IHJlc2V0X2NvbnRyb2wgICAgICAgICAgICAqcnN0 Owo+ICsgICAgICAgc3RydWN0IGdwaW9fZGVzYyAgICAgICAgICAgICAgICAqcnN0X2dwaW87Cj4g KyAgICAgICBzdHJ1Y3QgcmVndWxhdG9yICAgICAgICAgICAgICAgICp2cGNpZTN2MzsKPiArfTsK PiArCj4gK3N0YXRpYyBpbnQgcm9ja2NoaXBfcGNpZV9yZWFkbF9hcGIoc3RydWN0IHJvY2tjaGlw X3BjaWUgKnJvY2tjaGlwLAo+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIHUzMiByZWcpCj4gK3sKPiArICAgICAgIHJldHVybiByZWFkbChyb2NrY2hpcC0+YXBi X2Jhc2UgKyByZWcpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCByb2NrY2hpcF9wY2llX3dyaXRl bF9hcGIoc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwLAo+ICsgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHUzMiB2YWwsIHUzMiByZWcpCj4gK3sKPiAr ICAgICAgIHdyaXRlbCh2YWwsIHJvY2tjaGlwLT5hcGJfYmFzZSArIHJlZyk7Cj4gK30KPiArCj4g K3N0YXRpYyB2b2lkIHJvY2tjaGlwX3BjaWVfZW5hYmxlX2x0c3NtKHN0cnVjdCByb2NrY2hpcF9w Y2llICpyb2NrY2hpcCkKPiArewo+ICsgICAgICAgcm9ja2NoaXBfcGNpZV93cml0ZWxfYXBiKHJv Y2tjaGlwLCBQQ0lFX0NMSUVOVF9FTkFCTEVfTFRTU00sCj4gKyAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgUENJRV9DTElFTlRfR0VORVJBTF9DT05UUk9MKTsKPiArfQo+ICsKPiArc3Rh dGljIGludCByb2NrY2hpcF9wY2llX2xpbmtfdXAoc3RydWN0IGR3X3BjaWUgKnBjaSkKPiArewo+ ICsgICAgICAgc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwID0gdG9fcm9ja2NoaXBfcGNp ZShwY2kpOwo+ICsgICAgICAgdTMyIHZhbCA9IHJvY2tjaGlwX3BjaWVfcmVhZGxfYXBiKHJvY2tj aGlwLCBQQ0lFX0NMSUVOVF9MVFNTTV9TVEFUVVMpOwo+ICsKPiArICAgICAgIGlmICgodmFsICYg KFBDSUVfUkRMSF9MSU5LVVAgfCBQQ0lFX1NNTEhfTElOS1VQKSkgPT0gUENJRV9MSU5LVVAgJiYK PiArICAgICAgICAgICAodmFsICYgR0VOTUFTSyg1LCAwKSkgPT0gUENJRV9MMFNfRU5UUlkpCj4g KyAgICAgICAgICAgICAgIHJldHVybiAxOwo+ICsKPiArICAgICAgIHJldHVybiAwOwo+ICt9Cj4g Kwo+ICtzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfc3RhcnRfbGluayhzdHJ1Y3QgZHdfcGNpZSAq cGNpKQo+ICt7Cj4gKyAgICAgICBzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2NoaXAgPSB0b19y b2NrY2hpcF9wY2llKHBjaSk7Cj4gKwo+ICsgICAgICAgLyogUmVzZXQgZGV2aWNlICovCj4gKyAg ICAgICBncGlvZF9zZXRfdmFsdWVfY2Fuc2xlZXAocm9ja2NoaXAtPnJzdF9ncGlvLCAwKTsKPiAr Cj4gKyAgICAgICByb2NrY2hpcF9wY2llX2VuYWJsZV9sdHNzbShyb2NrY2hpcCk7Cj4gKwo+ICsg ICAgICAgLyoKPiArICAgICAgICAqIFBDSWUgcmVxdWlyZXMgdGhlIHJlZmNsayB0byBiZSBzdGFi bGUgZm9yIDEwMMK1cyBwcmlvciB0byByZWxlYXNpbmcKPiArICAgICAgICAqIFBFUlNULiBTZWUg dGFibGUgMi00IGluIHNlY3Rpb24gMi42LjIgQUMgU3BlY2lmaWNhdGlvbnMgb2YgdGhlIFBDSQo+ ICsgICAgICAgICogRXhwcmVzcyBDYXJkIEVsZWN0cm9tZWNoYW5pY2FsIFNwZWNpZmljYXRpb24s IDEuMS4gSG93ZXZlciwgd2UgZG9uJ3QKPiArICAgICAgICAqIGtub3cgaWYgdGhlIHJlZmNsayBp cyBjb21pbmcgZnJvbSBSQydzIFBIWSBvciBleHRlcm5hbCBPU0MuIElmIGl0J3MKPiArICAgICAg ICAqIGZyb20gUkMsIHNvIGVuYWJsaW5nIExUU1NNIGlzIHRoZSBqdXN0IHJpZ2h0IHBsYWNlIHRv IHJlbGVhc2UgI1BFUlNULgo+ICsgICAgICAgICogV2UgbmVlZCBtb3JlIGV4dHJhIHRpbWUgYXMg YmVmb3JlLCByYXRoZXIgdGhhbiBzZXR0aW5nIGp1c3QKPiArICAgICAgICAqIDEwMHVzIGFzIHdl IGRvbid0IGtub3cgaG93IGxvbmcgc2hvdWxkIHRoZSBkZXZpY2UgbmVlZCB0byByZXNldC4KPiAr ICAgICAgICAqLwo+ICsgICAgICAgbXNsZWVwKDEwMCk7Cj4gKyAgICAgICBncGlvZF9zZXRfdmFs dWVfY2Fuc2xlZXAocm9ja2NoaXAtPnJzdF9ncGlvLCAxKTsKPiArCj4gKyAgICAgICByZXR1cm4g MDsKPiArfQo+ICsKPiArc3RhdGljIGludCByb2NrY2hpcF9wY2llX2hvc3RfaW5pdChzdHJ1Y3Qg cGNpZV9wb3J0ICpwcCkKPiArewo+ICsgICAgICAgc3RydWN0IGR3X3BjaWUgKnBjaSA9IHRvX2R3 X3BjaWVfZnJvbV9wcChwcCk7Cj4gKyAgICAgICBzdHJ1Y3Qgcm9ja2NoaXBfcGNpZSAqcm9ja2No aXAgPSB0b19yb2NrY2hpcF9wY2llKHBjaSk7Cj4gKyAgICAgICB1MzIgdmFsOwo+ICsKPiArICAg ICAgIC8qIExUU1NNIGVuYWJsZSBjb250cm9sIG1vZGUgKi8KPiArICAgICAgIHZhbCA9IHJvY2tj aGlwX3BjaWVfcmVhZGxfYXBiKHJvY2tjaGlwLCBQQ0lFX0NMSUVOVF9IT1RfUkVTRVRfQ1RSTCk7 Cj4gKyAgICAgICB2YWwgfD0gUENJRV9MVFNTTV9FTkFCTEVfRU5IQU5DRSB8IChQQ0lFX0xUU1NN X0VOQUJMRV9FTkhBTkNFIDw8IDE2KTsKPiArICAgICAgIHJvY2tjaGlwX3BjaWVfd3JpdGVsX2Fw Yihyb2NrY2hpcCwgdmFsLCBQQ0lFX0NMSUVOVF9IT1RfUkVTRVRfQ1RSTCk7Cj4gKwo+ICsgICAg ICAgcm9ja2NoaXBfcGNpZV93cml0ZWxfYXBiKHJvY2tjaGlwLCBQQ0lFX0NMSUVOVF9SQ19NT0RF LAo+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFBDSUVfQ0xJRU5UX0dFTkVSQUxf Q09OVFJPTCk7Cj4gKwo+ICsgICAgICAgcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBjb25z dCBzdHJ1Y3QgZHdfcGNpZV9ob3N0X29wcyByb2NrY2hpcF9wY2llX2hvc3Rfb3BzID0gewo+ICsg ICAgICAgLmhvc3RfaW5pdCA9IHJvY2tjaGlwX3BjaWVfaG9zdF9pbml0LAo+ICt9Owo+ICsKPiAr c3RhdGljIGludCByb2NrY2hpcF9wY2llX2Nsa19pbml0KHN0cnVjdCByb2NrY2hpcF9wY2llICpy b2NrY2hpcCkKPiArewo+ICsgICAgICAgc3RydWN0IGRldmljZSAqZGV2ID0gcm9ja2NoaXAtPnBj aS5kZXY7Cj4gKyAgICAgICBpbnQgcmV0Owo+ICsKPiArICAgICAgIHJldCA9IGRldm1fY2xrX2J1 bGtfZ2V0X2FsbChkZXYsICZyb2NrY2hpcC0+Y2xrcyk7Cj4gKyAgICAgICBpZiAocmV0IDwgMCkK PiArICAgICAgICAgICAgICAgcmV0dXJuIHJldDsKPiArCj4gKyAgICAgICByb2NrY2hpcC0+Y2xr X2NudCA9IHJldDsKPiArCj4gKyAgICAgICByZXR1cm4gY2xrX2J1bGtfcHJlcGFyZV9lbmFibGUo cm9ja2NoaXAtPmNsa19jbnQsIHJvY2tjaGlwLT5jbGtzKTsKPiArfQo+ICsKPiArc3RhdGljIGlu dCByb2NrY2hpcF9wY2llX3Jlc291cmNlX2dldChzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2 LAo+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IHJvY2tjaGlw X3BjaWUgKnJvY2tjaGlwKQo+ICt7Cj4gKyAgICAgICByb2NrY2hpcC0+YXBiX2Jhc2UgPSBkZXZt X3BsYXRmb3JtX2lvcmVtYXBfcmVzb3VyY2VfYnluYW1lKHBkZXYsICJhcGIiKTsKPiArICAgICAg IGlmIChJU19FUlIocm9ja2NoaXAtPmFwYl9iYXNlKSkKPiArICAgICAgICAgICAgICAgcmV0dXJu IFBUUl9FUlIocm9ja2NoaXAtPmFwYl9iYXNlKTsKPiArCj4gKyAgICAgICByb2NrY2hpcC0+cnN0 X2dwaW8gPSBkZXZtX2dwaW9kX2dldF9vcHRpb25hbCgmcGRldi0+ZGV2LCAicmVzZXQiLAo+ICsg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgR1BJT0Rf T1VUX0hJR0gpOwo+ICsgICAgICAgaWYgKElTX0VSUihyb2NrY2hpcC0+cnN0X2dwaW8pKQo+ICsg ICAgICAgICAgICAgICByZXR1cm4gUFRSX0VSUihyb2NrY2hpcC0+cnN0X2dwaW8pOwo+ICsKPiAr ICAgICAgIHJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfcGh5 X2luaXQoc3RydWN0IHJvY2tjaGlwX3BjaWUgKnJvY2tjaGlwKQo+ICt7Cj4gKyAgICAgICBzdHJ1 Y3QgZGV2aWNlICpkZXYgPSByb2NrY2hpcC0+cGNpLmRldjsKPiArICAgICAgIGludCByZXQ7Cj4g Kwo+ICsgICAgICAgcm9ja2NoaXAtPnBoeSA9IGRldm1fcGh5X2dldChkZXYsICJwY2llLXBoeSIp Owo+ICsgICAgICAgaWYgKElTX0VSUihyb2NrY2hpcC0+cGh5KSkKPiArICAgICAgICAgICAgICAg cmV0dXJuIGRldl9lcnJfcHJvYmUoZGV2LCBQVFJfRVJSKHJvY2tjaGlwLT5waHkpLAo+ICsgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAibWlzc2luZyBQSFlcbiIpOwo+ICsKPiAr ICAgICAgIHJldCA9IHBoeV9pbml0KHJvY2tjaGlwLT5waHkpOwo+ICsgICAgICAgaWYgKHJldCA8 IDApCj4gKyAgICAgICAgICAgICAgIHJldHVybiByZXQ7Cj4gKwo+ICsgICAgICAgcmV0ID0gcGh5 X3Bvd2VyX29uKHJvY2tjaGlwLT5waHkpOwo+ICsgICAgICAgaWYgKHJldCkKPiArICAgICAgICAg ICAgICAgcGh5X2V4aXQocm9ja2NoaXAtPnBoeSk7Cj4gKwo+ICsgICAgICAgcmV0dXJuIHJldDsK PiArfQo+ICsKPiArc3RhdGljIHZvaWQgcm9ja2NoaXBfcGNpZV9waHlfZGVpbml0KHN0cnVjdCBy b2NrY2hpcF9wY2llICpyb2NrY2hpcCkKPiArewo+ICsgICAgICAgcGh5X2V4aXQocm9ja2NoaXAt PnBoeSk7Cj4gKyAgICAgICBwaHlfcG93ZXJfb2ZmKHJvY2tjaGlwLT5waHkpOwo+ICt9Cj4gKwo+ ICtzdGF0aWMgaW50IHJvY2tjaGlwX3BjaWVfcmVzZXRfY29udHJvbF9yZWxlYXNlKHN0cnVjdCBy b2NrY2hpcF9wY2llICpyb2NrY2hpcCkKPiArewo+ICsgICAgICAgc3RydWN0IGRldmljZSAqZGV2 ID0gcm9ja2NoaXAtPnBjaS5kZXY7Cj4gKwo+ICsgICAgICAgcm9ja2NoaXAtPnJzdCA9IGRldm1f cmVzZXRfY29udHJvbF9hcnJheV9nZXRfZXhjbHVzaXZlKGRldik7Cj4gKyAgICAgICBpZiAoSVNf RVJSKHJvY2tjaGlwLT5yc3QpKQo+ICsgICAgICAgICAgICAgICByZXR1cm4gZGV2X2Vycl9wcm9i ZShkZXYsIFBUUl9FUlIocm9ja2NoaXAtPnJzdCksCj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICJmYWlsZWQgdG8gZ2V0IHJlc2V0IGxpbmVzXG4iKTsKPiArCj4gKyAgICAg ICByZXR1cm4gcmVzZXRfY29udHJvbF9kZWFzc2VydChyb2NrY2hpcC0+cnN0KTsKPiArfQo+ICsK PiArc3RhdGljIGNvbnN0IHN0cnVjdCBkd19wY2llX29wcyBkd19wY2llX29wcyA9IHsKPiArICAg ICAgIC5saW5rX3VwID0gcm9ja2NoaXBfcGNpZV9saW5rX3VwLAo+ICsgICAgICAgLnN0YXJ0X2xp bmsgPSByb2NrY2hpcF9wY2llX3N0YXJ0X2xpbmssCj4gK307Cj4gKwo+ICtzdGF0aWMgaW50IHJv Y2tjaGlwX3BjaWVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsg ICAgICAgc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiArICAgICAgIHN0cnVjdCBy b2NrY2hpcF9wY2llICpyb2NrY2hpcDsKPiArICAgICAgIHN0cnVjdCBwY2llX3BvcnQgKnBwOwo+ ICsgICAgICAgaW50IHJldDsKPiArCj4gKyAgICAgICByb2NrY2hpcCA9IGRldm1fa3phbGxvYyhk ZXYsIHNpemVvZigqcm9ja2NoaXApLCBHRlBfS0VSTkVMKTsKPiArICAgICAgIGlmICghcm9ja2No aXApCj4gKyAgICAgICAgICAgICAgIHJldHVybiAtRU5PTUVNOwo+ICsKPiArICAgICAgIHBsYXRm b3JtX3NldF9kcnZkYXRhKHBkZXYsIHJvY2tjaGlwKTsKPiArCj4gKyAgICAgICByb2NrY2hpcC0+ cGNpLmRldiA9IGRldjsKPiArICAgICAgIHJvY2tjaGlwLT5wY2kub3BzID0gJmR3X3BjaWVfb3Bz Owo+ICsKPiArICAgICAgIHBwID0gJnJvY2tjaGlwLT5wY2kucHA7Cj4gKyAgICAgICBwcC0+b3Bz ID0gJnJvY2tjaGlwX3BjaWVfaG9zdF9vcHM7Cj4gKwo+ICsgICAgICAgcmV0ID0gcm9ja2NoaXBf cGNpZV9yZXNvdXJjZV9nZXQocGRldiwgcm9ja2NoaXApOwo+ICsgICAgICAgaWYgKHJldCkKPiAr ICAgICAgICAgICAgICAgcmV0dXJuIHJldDsKPiArCj4gKyAgICAgICAvKiBET04nVCBNT1ZFIE1F OiBtdXN0IGJlIGVuYWJsZSBiZWZvcmUgUEhZIGluaXQgKi8KPiArICAgICAgIHJvY2tjaGlwLT52 cGNpZTN2MyA9IGRldm1fcmVndWxhdG9yX2dldF9vcHRpb25hbChkZXYsICJ2cGNpZTN2MyIpOwo+ ICsgICAgICAgaWYgKElTX0VSUihyb2NrY2hpcC0+dnBjaWUzdjMpKQo+ICsgICAgICAgICAgICAg ICBpZiAoUFRSX0VSUihyb2NrY2hpcC0+dnBjaWUzdjMpICE9IC1FTk9ERVYpCj4gKyAgICAgICAg ICAgICAgICAgICAgICAgcmV0dXJuIGRldl9lcnJfcHJvYmUoZGV2LCBQVFJfRVJSKHJvY2tjaGlw LT52cGNpZTN2MyksCj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICJm YWlsZWQgdG8gZ2V0IHZwY2llM3YzIHJlZ3VsYXRvclxuIik7Cj4gKwo+ICsgICAgICAgcmV0ID0g cmVndWxhdG9yX2VuYWJsZShyb2NrY2hpcC0+dnBjaWUzdjMpOwo+ICsgICAgICAgaWYgKHJldCkg ewo+ICsgICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgImZhaWxlZCB0byBlbmFibGUgdnBjaWUz djMgcmVndWxhdG9yXG4iKTsKPiArICAgICAgICAgICAgICAgcmV0dXJuIHJldDsKPiArICAgICAg IH0KPiArCj4gKyAgICAgICByZXQgPSByb2NrY2hpcF9wY2llX3BoeV9pbml0KHJvY2tjaGlwKTsK PiArICAgICAgIGlmIChyZXQpCj4gKyAgICAgICAgICAgICAgIGdvdG8gZGlzYWJsZV9yZWd1bGF0 b3I7Cj4gKwo+ICsgICAgICAgcmV0ID0gcm9ja2NoaXBfcGNpZV9yZXNldF9jb250cm9sX3JlbGVh c2Uocm9ja2NoaXApOwo+ICsgICAgICAgaWYgKHJldCkKPiArICAgICAgICAgICAgICAgZ290byBk ZWluaXRfcGh5Owo+ICsKPiArICAgICAgIHJldCA9IHJvY2tjaGlwX3BjaWVfY2xrX2luaXQocm9j a2NoaXApOwo+ICsgICAgICAgaWYgKHJldCkKPiArICAgICAgICAgICAgICAgZ290byBkZWluaXRf cGh5Owo+ICsKPiArICAgICAgIHJldCA9IGR3X3BjaWVfaG9zdF9pbml0KHBwKTsKPiArICAgICAg IGlmICghcmV0KQo+ICsgICAgICAgICAgICAgICByZXR1cm4gMDsKPiArCj4gKyAgICAgICBjbGtf YnVsa19kaXNhYmxlX3VucHJlcGFyZShyb2NrY2hpcC0+Y2xrX2NudCwgcm9ja2NoaXAtPmNsa3Mp Owo+ICtkZWluaXRfcGh5Ogo+ICsgICAgICAgcm9ja2NoaXBfcGNpZV9waHlfZGVpbml0KHJvY2tj aGlwKTsKPiArZGlzYWJsZV9yZWd1bGF0b3I6Cj4gKyAgICAgICByZWd1bGF0b3JfZGlzYWJsZShy b2NrY2hpcC0+dnBjaWUzdjMpOwo+ICsKPiArICAgICAgIHJldHVybiByZXQ7Cj4gK30KPiArCj4g K3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIHJvY2tjaGlwX3BjaWVfb2ZfbWF0Y2hb XSA9IHsKPiArICAgICAgIHsgLmNvbXBhdGlibGUgPSAicm9ja2NoaXAscmszNTY4LXBjaWUiLCB9 LAo+ICsgICAgICAge30sCj4gK307Cj4gKwo+ICtzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZl ciByb2NrY2hpcF9wY2llX2RyaXZlciA9IHsKPiArICAgICAgIC5kcml2ZXIgPSB7Cj4gKyAgICAg ICAgICAgICAgIC5uYW1lICAgPSAicm9ja2NoaXAtZHctcGNpZSIsCj4gKyAgICAgICAgICAgICAg IC5vZl9tYXRjaF90YWJsZSA9IHJvY2tjaGlwX3BjaWVfb2ZfbWF0Y2gsCj4gKyAgICAgICAgICAg ICAgIC5zdXBwcmVzc19iaW5kX2F0dHJzID0gdHJ1ZSwKPiArICAgICAgIH0sCj4gKyAgICAgICAu cHJvYmUgPSByb2NrY2hpcF9wY2llX3Byb2JlLAo+ICt9Owo+ICtidWlsdGluX3BsYXRmb3JtX2Ry aXZlcihyb2NrY2hpcF9wY2llX2RyaXZlcik7Cj4gLS0KPiAyLjI1LjEKPgo+Cj4KPgo+IF9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gTGludXgtcm9ja2No aXAgbWFpbGluZyBsaXN0Cj4gTGludXgtcm9ja2NoaXBAbGlzdHMuaW5mcmFkZWFkLm9yZwo+IGh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4LXJv Y2tjaGlwIG1haWxpbmcgbGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK