From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A016C43219 for ; Mon, 30 May 2022 14:53:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239847AbiE3Owo (ORCPT ); Mon, 30 May 2022 10:52:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242707AbiE3Ob3 (ORCPT ); Mon, 30 May 2022 10:31:29 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD5DB85ECA; Mon, 30 May 2022 06:53:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A180A61036; Mon, 30 May 2022 13:53:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 148EEC36AEB; Mon, 30 May 2022 13:53:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653918790; bh=Y95uwozMiasRFvhxXf2nNnDa5yGqC+rlAQxH7OwKqN8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=G/I1BvxjIJNL5l5XSD1i06sB0VTZ4hiDWnlDz2QT88os6ckOPH+K+B/GLzR4nQBVi O1RaV5gl/qoivUgTBS2RBghDeCpeLq/ejfTiLwd6Exm8YAWjTHGs0hrGZ7kvOQeziA nudFe4LqcpvPbMVQVfWxjePpG0MpDYtImrl5FymQhRcI/ZL/pcDLsDSDgJnbAXea1I aHYwr52uj42oTqQ0ZrA1U/VjhD4Hvup3idBhwxFC+Ak4v6ySqJdj7+FvaygNc046YE Ql6FX/lAkauFVAC2SzLOQ1UK4CfgMm+v8iEUpOWNdf/7d99zQ5/Qafe5zC3dRa7XbO AzV1hadzN/dRA== Received: by mail-ot1-f42.google.com with SMTP id c15-20020a9d684f000000b0060b097c71ecso7686291oto.10; Mon, 30 May 2022 06:53:10 -0700 (PDT) X-Gm-Message-State: AOAM533n+Mn7XNokRhi+MzXq3V7E2qmI83j5ZnUZ5WEuIkCU7LnIIi4Y EaPXwKJXSVNSrkp8VzWBOvljympAKHFldhA6kBU= X-Google-Smtp-Source: ABdhPJxPLLr1XoxeuO67R+Z55CuEL035Z/P4lQH8hSWDB5SwljRju1yg2WNI/wdi+r9DZDAx+qZm+isA15gpogCxYxI= X-Received: by 2002:a05:6830:9c2:b0:606:1e0a:cc8d with SMTP id y2-20020a05683009c200b006061e0acc8dmr20945598ott.265.1653918789233; Mon, 30 May 2022 06:53:09 -0700 (PDT) MIME-Version: 1.0 References: <20220530134406.1934928-1-sashal@kernel.org> <20220530134406.1934928-69-sashal@kernel.org> In-Reply-To: <20220530134406.1934928-69-sashal@kernel.org> From: Ard Biesheuvel Date: Mon, 30 May 2022 15:52:58 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH AUTOSEL 5.10 69/76] ARM: 9201/1: spectre-bhb: rely on linker to emit cross-section literal loads To: Sasha Levin Cc: Linux Kernel Mailing List , "# 3.4.x" , Russell King , Russell King , Linus Walleij , Nicolas Pitre , Arnd Bergmann , Linux ARM Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AUTONAK On Mon, 30 May 2022 at 15:46, Sasha Levin wrote: > > From: Ard Biesheuvel > > [ Upstream commit ad12c2f1587c6ec9b52ff226f438955bfae6ad89 ] > > The assembler does not permit 'LDR PC, ' when the symbol lives in a > different section, which is why we have been relying on rather fragile > open-coded arithmetic to load the address of the vector_swi routine into > the program counter using a single LDR instruction in the SWI slot in > the vector table. The literal was moved to a different section to in > commit 19accfd373847 ("ARM: move vector stubs") to ensure that the > vector stubs page does not need to be mapped readable for user space, > which is the case for the vector page itself, as it carries the kuser > helpers as well. > > So the cross-section literal load is open-coded, and this relies on the > address of vector_swi to be at the very start of the vector stubs page, > and we won't notice if we got it wrong until booting the kernel and see > it break. Fortunately, it was guaranteed to break, so this was fragile > but not problematic. > > Now that we have added two other variants of the vector table, we have 3 > occurrences of the same trick, and so the size of our ISA/compiler/CPU > validation space has tripled, in a way that may cause regressions to only > be observed once booting the image in question on a CPU that exercises a > particular vector table. > > So let's switch to true cross section references, and let the linker fix > them up like it fixes up all the other cross section references in the > vector page. > > Signed-off-by: Ard Biesheuvel > Signed-off-by: Russell King (Oracle) > Signed-off-by: Sasha Levin > --- > arch/arm/kernel/entry-armv.S | 22 +++++++++++++++------- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S > index 030351d169aa..aad77ad97d5f 100644 > --- a/arch/arm/kernel/entry-armv.S > +++ b/arch/arm/kernel/entry-armv.S > @@ -1074,10 +1074,15 @@ ENDPROC(vector_bhb_bpiall_\name) > .endm > > .section .stubs, "ax", %progbits > - @ This must be the first word > + @ These need to remain at the start of the section so that > + @ they are in range of the 'SWI' entries in the vector tables > + @ located 4k down. > +.L__vector_swi: > .word vector_swi > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > +.L__vector_bhb_loop8_swi: > .word vector_bhb_loop8_swi > +.L__vector_bhb_bpiall_swi: > .word vector_bhb_bpiall_swi > #endif > > @@ -1220,10 +1225,11 @@ vector_addrexcptn: > .globl vector_fiq > > .section .vectors, "ax", %progbits > -.L__vectors_start: > W(b) vector_rst > W(b) vector_und > - W(ldr) pc, .L__vectors_start + 0x1000 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) > + W(ldr) pc, . > W(b) vector_pabt > W(b) vector_dabt > W(b) vector_addrexcptn > @@ -1232,10 +1238,11 @@ vector_addrexcptn: > > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > .section .vectors.bhb.loop8, "ax", %progbits > -.L__vectors_bhb_loop8_start: > W(b) vector_rst > W(b) vector_bhb_loop8_und > - W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) > + W(ldr) pc, . > W(b) vector_bhb_loop8_pabt > W(b) vector_bhb_loop8_dabt > W(b) vector_addrexcptn > @@ -1243,10 +1250,11 @@ vector_addrexcptn: > W(b) vector_bhb_loop8_fiq > > .section .vectors.bhb.bpiall, "ax", %progbits > -.L__vectors_bhb_bpiall_start: > W(b) vector_rst > W(b) vector_bhb_bpiall_und > - W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi ) > + W(ldr) pc, . > W(b) vector_bhb_bpiall_pabt > W(b) vector_bhb_bpiall_dabt > W(b) vector_addrexcptn > -- > 2.35.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A4AAC433F5 for ; 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Mon, 30 May 2022 06:53:10 -0700 (PDT) X-Gm-Message-State: AOAM530SFXamvBWKfBAKlA/BeJfAJ3XKJ9beZxuvBo4/nagJ8Ga/G4Rd tcQbB9MMFK/qNC6pVR3bpaTYfAqhyUmio3xWNyw= X-Google-Smtp-Source: ABdhPJxPLLr1XoxeuO67R+Z55CuEL035Z/P4lQH8hSWDB5SwljRju1yg2WNI/wdi+r9DZDAx+qZm+isA15gpogCxYxI= X-Received: by 2002:a05:6830:9c2:b0:606:1e0a:cc8d with SMTP id y2-20020a05683009c200b006061e0acc8dmr20945598ott.265.1653918789233; Mon, 30 May 2022 06:53:09 -0700 (PDT) MIME-Version: 1.0 References: <20220530134406.1934928-1-sashal@kernel.org> <20220530134406.1934928-69-sashal@kernel.org> In-Reply-To: <20220530134406.1934928-69-sashal@kernel.org> From: Ard Biesheuvel Date: Mon, 30 May 2022 15:52:58 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH AUTOSEL 5.10 69/76] ARM: 9201/1: spectre-bhb: rely on linker to emit cross-section literal loads To: Sasha Levin Cc: Linux Kernel Mailing List , "# 3.4.x" , Russell King , Russell King , Linus Walleij , Nicolas Pitre , Arnd Bergmann , Linux ARM X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220530_065312_292084_4A7DEB05 X-CRM114-Status: GOOD ( 31.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org AUTONAK On Mon, 30 May 2022 at 15:46, Sasha Levin wrote: > > From: Ard Biesheuvel > > [ Upstream commit ad12c2f1587c6ec9b52ff226f438955bfae6ad89 ] > > The assembler does not permit 'LDR PC, ' when the symbol lives in a > different section, which is why we have been relying on rather fragile > open-coded arithmetic to load the address of the vector_swi routine into > the program counter using a single LDR instruction in the SWI slot in > the vector table. The literal was moved to a different section to in > commit 19accfd373847 ("ARM: move vector stubs") to ensure that the > vector stubs page does not need to be mapped readable for user space, > which is the case for the vector page itself, as it carries the kuser > helpers as well. > > So the cross-section literal load is open-coded, and this relies on the > address of vector_swi to be at the very start of the vector stubs page, > and we won't notice if we got it wrong until booting the kernel and see > it break. Fortunately, it was guaranteed to break, so this was fragile > but not problematic. > > Now that we have added two other variants of the vector table, we have 3 > occurrences of the same trick, and so the size of our ISA/compiler/CPU > validation space has tripled, in a way that may cause regressions to only > be observed once booting the image in question on a CPU that exercises a > particular vector table. > > So let's switch to true cross section references, and let the linker fix > them up like it fixes up all the other cross section references in the > vector page. > > Signed-off-by: Ard Biesheuvel > Signed-off-by: Russell King (Oracle) > Signed-off-by: Sasha Levin > --- > arch/arm/kernel/entry-armv.S | 22 +++++++++++++++------- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S > index 030351d169aa..aad77ad97d5f 100644 > --- a/arch/arm/kernel/entry-armv.S > +++ b/arch/arm/kernel/entry-armv.S > @@ -1074,10 +1074,15 @@ ENDPROC(vector_bhb_bpiall_\name) > .endm > > .section .stubs, "ax", %progbits > - @ This must be the first word > + @ These need to remain at the start of the section so that > + @ they are in range of the 'SWI' entries in the vector tables > + @ located 4k down. > +.L__vector_swi: > .word vector_swi > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > +.L__vector_bhb_loop8_swi: > .word vector_bhb_loop8_swi > +.L__vector_bhb_bpiall_swi: > .word vector_bhb_bpiall_swi > #endif > > @@ -1220,10 +1225,11 @@ vector_addrexcptn: > .globl vector_fiq > > .section .vectors, "ax", %progbits > -.L__vectors_start: > W(b) vector_rst > W(b) vector_und > - W(ldr) pc, .L__vectors_start + 0x1000 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) > + W(ldr) pc, . > W(b) vector_pabt > W(b) vector_dabt > W(b) vector_addrexcptn > @@ -1232,10 +1238,11 @@ vector_addrexcptn: > > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > .section .vectors.bhb.loop8, "ax", %progbits > -.L__vectors_bhb_loop8_start: > W(b) vector_rst > W(b) vector_bhb_loop8_und > - W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) > + W(ldr) pc, . > W(b) vector_bhb_loop8_pabt > W(b) vector_bhb_loop8_dabt > W(b) vector_addrexcptn > @@ -1243,10 +1250,11 @@ vector_addrexcptn: > W(b) vector_bhb_loop8_fiq > > .section .vectors.bhb.bpiall, "ax", %progbits > -.L__vectors_bhb_bpiall_start: > W(b) vector_rst > W(b) vector_bhb_bpiall_und > - W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi ) > + W(ldr) pc, . > W(b) vector_bhb_bpiall_pabt > W(b) vector_bhb_bpiall_dabt > W(b) vector_addrexcptn > -- > 2.35.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel