From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3F19C433F5 for ; Wed, 13 Apr 2022 17:34:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A++NfvlFmbTrBpGyY2/WAOwqxeXf6Qf1Q9PRRbAVXco=; b=Qr62eP9eK2LDFI qnWoug9KAdeVMEghxrvdAeqBcmdRt68NltX5m1x5HVH7p9IRa7LdIZYfB3Sy+xR3TWgeE/oLZl3UX jHi36T8+ojgo0W3YL34nu2seXrK6Cq2fkQwQT32THfElzu6mNJ8p9ZAb9kG+ulWAWMQIj052Tutwt wSp2dv9zh7vhUF+aRJ7XZKNp12S9EVI/fl625O+VQPVP6iLAi6qWHBcgs+kOjfDM7RZmrGgiybCLd lJQmUyzXBnriWHPvGQUhEwUttbNHhzYfO1q+IqOCbOz9MDlsPPpXbKb89yMN1UVCqiQps4UdhtRoe upsT4ceH1AR4YLLJqs4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1negru-001wek-Lc; Wed, 13 Apr 2022 17:33:26 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1negrq-001wde-9u for linux-arm-kernel@lists.infradead.org; Wed, 13 Apr 2022 17:33:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9F174B825E5 for ; Wed, 13 Apr 2022 17:33:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FA59C385A4 for ; Wed, 13 Apr 2022 17:33:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649871199; bh=I2qMnIMkbQq04yNIhJRIhOv/wVxSHvswJpHhN34oJ6M=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Ng66lVs6K5jlXcyQfUO63Eg+gZms0v4988wn51+zP+3s6dYhnk/2jlL9JPRTCfe7R g6S5OVr1sfRWUbqYn8YdjGckhbbRjyV+fvXaCFiLEjMmyB0hINSGfSJcnFZjoIDxVU ZkBmoKs6GnBq0Jo0h1VgW0JfdTCGEFvnmTW7YOqJIaMP71Wg10xiDlJkd9zXp9hMTS xvjkMQBoMHkYKq+SHchMIroGUSf4X2DuVVRd3eXyrfv9q4UKo+imEvFs4R1cxu4U9E LTq+2VBSKTG8oqdM7qa5TkeGlSYPw4QFkv39kRapD+HjXr0pVvMv7wMhAZGnWzRVYV xN8y7ZvkfJjyw== Received: by mail-oa1-f49.google.com with SMTP id 586e51a60fabf-de3eda6b5dso2774226fac.0 for ; Wed, 13 Apr 2022 10:33:19 -0700 (PDT) X-Gm-Message-State: AOAM5336GrqPgtEBkYFHtIJfDHyDKUIiuvuq31CForNuuKWpSk78PTcZ S04S3FzjMOg+MzwJTcElfqvu5KNe6MrfVMcSUS4= X-Google-Smtp-Source: ABdhPJztUsDMljoUiaWLPQld++j/VMjQr3AuAAeCOnFPrIG5TlEWCQ3BwDJPy2J+IYfccxU21hCI1ZYnsvS5UVI0Row= X-Received: by 2002:a05:6870:eaa5:b0:da:b3f:2b45 with SMTP id s37-20020a056870eaa500b000da0b3f2b45mr221oap.228.1649871198320; Wed, 13 Apr 2022 10:33:18 -0700 (PDT) MIME-Version: 1.0 References: <20220413170545.3042558-1-james.morse@arm.com> <20220413170545.3042558-2-james.morse@arm.com> In-Reply-To: <20220413170545.3042558-2-james.morse@arm.com> From: Ard Biesheuvel Date: Wed, 13 Apr 2022 19:33:06 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/2] arm64: errata: Remove AES hwcap for COMPAT tasks To: James Morse Cc: Linux ARM , Russell King , Catalin Marinas , Will Deacon X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220413_103322_674747_914A1562 X-CRM114-Status: GOOD ( 35.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On Wed, 13 Apr 2022 at 19:06, James Morse wrote: > > Cortex-A57 and Cortex-A72 have an erratum where an interrupt that > occurs between a pair of AES instructions in aarch32 mode may corrupt > the ELR. The task will subsequently produce the wrong AES result. > > The AES instructions are part of the cryptographic extensions, which are > optional. User-space software will detect the support for these > instructions from the hwcaps. If the platform doesn't support these > instructions a software implementation should be used. > > Remove the hwcap bits on affected parts to indicate user-space should > not use the AES instructions. > > Signed-off-by: James Morse Acked-by: Ard Biesheuvel One nit/question below, > --- > Documentation/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ > arch/arm64/kernel/cpufeature.c | 11 ++++++++++- > arch/arm64/tools/cpucaps | 1 + > 5 files changed, 47 insertions(+), 1 deletion(-) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 466cb9e89047..053dc12696b5 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -82,10 +82,14 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A72 | #853709 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 57c4c995965f..df19e60c4c46 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -491,6 +491,22 @@ config ARM64_ERRATUM_834220 > > If unsure, say Y. > > +config ARM64_ERRATUM_1742098 > + bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" > + depends on COMPAT > + default y > + help > + This option removes the AES hwcap for aarch32 user-space to > + workaround erratum 1742098 on Cortex-A57 and Cortex-A72. > + > + Affected parts may corrupt the AES state if an interrupt is > + taken between a pair of AES instructions. These instructions > + are only present if the cryptography extensions are present. > + All software should have a fallback implementation for CPUs > + that don't implement the cryptography extensions. > + > + If unsure, say Y. > + > config ARM64_ERRATUM_845719 > bool "Cortex-A53: 845719: a load might read incorrect data" > depends on COMPAT > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 4c9b5b4b7a0b..8f85dac4cd79 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -393,6 +393,14 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ > > +#ifdef CONFIG_ARM64_ERRATUM_1742098 > +static struct midr_range broken_aarch32_aes[] = { > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), Not sure it matters, but are you sure early A57 is affected as well? > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -655,6 +663,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > /* Cortex-A510 r0p0 - r0p1 */ > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_1742098 > + { > + .desc = "ARM erratum 1742098", > + .capability = ARM64_WORKAROUND_1742098, > + CAP_MIDR_RANGE_LIST(broken_aarch32_aes), > + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, > + }, > #endif > { > } > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index d72c4b4d389c..3faf16f1c040 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1922,6 +1922,12 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) > } > #endif /* CONFIG_ARM64_MTE */ > > +static void elf_hwcap_fixup(void) > +{ > + if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) > + compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; > +} > + > #ifdef CONFIG_KVM > static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) > { > @@ -3034,8 +3040,10 @@ void __init setup_cpu_features(void) > setup_system_capabilities(); > setup_elf_hwcaps(arm64_elf_hwcaps); > > - if (system_supports_32bit_el0()) > + if (system_supports_32bit_el0()) { > setup_elf_hwcaps(compat_elf_hwcaps); > + elf_hwcap_fixup(); > + } > > if (system_uses_ttbr0_pan()) > pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); > @@ -3087,6 +3095,7 @@ static int enable_mismatched_32bit_el0(unsigned int cpu) > cpu_active_mask); > get_cpu_device(lucky_winner)->offline_disabled = true; > setup_elf_hwcaps(compat_elf_hwcaps); > + elf_hwcap_fixup(); > pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", > cpu, lucky_winner); > return 0; > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 3ed418f70e3b..8cd6088f8875 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -58,6 +58,7 @@ WORKAROUND_1418040 > WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > +WORKAROUND_1742098 > WORKAROUND_1902691 > WORKAROUND_2038923 > WORKAROUND_2064142 > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel