From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC34C433DB for ; Fri, 22 Jan 2021 16:34:19 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D06CF239EE for ; Fri, 22 Jan 2021 16:34:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D06CF239EE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tQdqKMbXRQG33jcWym+8gYOBS6EtUz+V4WxN5yv9jJM=; b=GThGZebkVNs+aCXs+/+ydrnh3 wZhRs2SDVwfv/l4neH6WILYCO8QWIv91B1r7FrMUlp/Rlaz7zPCq50K5OfosoQ8SAgP9u++Xmct35 CcOK7RCT8zv5fOec0iletjc3izavfGh5277zFNHzt6RYmI/WHld+Q1NJrMPHjrH9Mnir1uYZyGnPg pEgasb1/mR4LPGVWG+0yU8CfFxqUrJ5tEL6ZqoGiUVbwZrivG5uQvHO01G7fQjCIDKeTbeB5CT4wJ xWho7prjASlZFxDHsjxwWLIQHpnonGvyfvI+PxgiGzND/5lzjQVinL6j6MpPGkrS9i8PLKZp32vp5 4EYzfWCEQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2zMP-0005yV-L3; Fri, 22 Jan 2021 16:32:33 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2zMN-0005xz-4K for linux-arm-kernel@lists.infradead.org; Fri, 22 Jan 2021 16:32:32 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id EAA3223A81 for ; Fri, 22 Jan 2021 16:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611333150; bh=A/9qXY/EQEwYJa+fVUVSFMNg4IGovs+JeXY1Tms/pwg=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=pXsXEluIgmYaiPaerxpYxdW4X8uH68+4UIHUWQ/xXCkdc21EmhfhltZVDABv2ZlUn 9jFvJcr7BH2xfabeL5A11rZUF7OBUjhqIWcamYeIEiTiuyaZNkQpJ8+ToAaf8hh1tU VppWNi3YduGnT2LEkvSfW8WRFA1smL1K4E4dlMGG55oddy2v5GUS+jItfucUW8OxKz PVLJarBPMXBEuwa6QBTevhLYJxJD6Kl4NZ/eSLmqn/FzCtpYyFj7KmBReCyoEhJ2wB UFElw18UtkvCBoZ9yCBkpks58SycnPG8urZXaC8/guWc6OFwRXlvI3Uzas5YX36Wm/ zazdZ4jwBTmMg== Received: by mail-oo1-f53.google.com with SMTP id u7so932583ooq.0 for ; Fri, 22 Jan 2021 08:32:29 -0800 (PST) X-Gm-Message-State: AOAM531GdZOUL02AXfVZEZzhEEyKjneN8AG6HbKI07lZSb0oy268XhIy wqyMW0DYWngzgPXM+4kofk9gYP8i+uJxaN2z+aA= X-Google-Smtp-Source: ABdhPJzaETik2cnfskfrnerY/X7sEzTAeq1hCaabvdCK69e4UK/c6GdMx0KYcBcfqbigl258n8GK4TkNyJ4Vh09YHHY= X-Received: by 2002:a4a:2a42:: with SMTP id x2mr1940920oox.41.1611333149225; Fri, 22 Jan 2021 08:32:29 -0800 (PST) MIME-Version: 1.0 References: <20210122152012.30075-1-ardb@kernel.org> <20210122161312.GS1551@shell.armlinux.org.uk> In-Reply-To: <20210122161312.GS1551@shell.armlinux.org.uk> From: Ard Biesheuvel Date: Fri, 22 Jan 2021 17:32:18 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] ARM: decompressor: cover BSS in cache clean and reorder with MMU disable on v7 To: Russell King - ARM Linux admin X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_113231_304906_23539F77 X-CRM114-Status: GOOD ( 26.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 22 Jan 2021 at 17:13, Russell King - ARM Linux admin wrote: > > On Fri, Jan 22, 2021 at 04:20:12PM +0100, Ard Biesheuvel wrote: > > To ensure that no cache lines cover any of the data that is accessed by > > the booting kernel with the MMU off, cover the uncompressed kernel's BSS > > region in the cache clean operation. > > > > Also, to ensure that no cachelines are allocated while the cache is being > > cleaned, perform the cache clean operation *after* disabling the MMU and > > caches when running on v7 or later, by making a tail call to the clean > > routine from the cache_off routine. This requires passing the VA range > > to cache_off(), which means some care needs to be taken to preserve > > R0 and R1 across the call to cache_off(). > > > > Since this makes the first cache clean redundant, call it with the > > range reduced to zero. This only affects v7, as all other versions > > ignore R0/R1 entirely. > > > > Signed-off-by: Ard Biesheuvel > > Seems to work, thanks! I'd suggest we follow up with this patch which > gets rid of all the register shuffling: > Agreed > 8<=== > From: Russell King > Subject: [PATCH] ARM: decompressor: tidy up register usage > > Tidy up the registers so we don't end up having to shuffle values > between registers to work around other register usages. > > Signed-off-by: Russell King Acked-by: Ard Biesheuvel > --- > arch/arm/boot/compressed/head.S | 41 +++++++++++++++------------------ > 1 file changed, 19 insertions(+), 22 deletions(-) > > diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S > index b44738110095..c0a13004c5d4 100644 > --- a/arch/arm/boot/compressed/head.S > +++ b/arch/arm/boot/compressed/head.S > @@ -930,6 +930,7 @@ ENDPROC(__setup_mmu) Can we drop the r1 = corrupted here now? > * r2 = corrupted > * r3 = block offset > * r9 = corrupted > + * r10 = corrupted > * r12 = corrupted > */ > > @@ -949,10 +950,10 @@ call_cache_fn: adr r12, proc_types > #else > ldr r9, =CONFIG_PROCESSOR_ID > #endif > -1: ldr r1, [r12, #0] @ get value > +1: ldr r10, [r12, #0] @ get value > ldr r2, [r12, #4] @ get mask > - eor r1, r1, r9 @ (real ^ match) > - tst r1, r2 @ & mask > + eor r10, r10, r9 @ (real ^ match) > + tst r10, r2 @ & mask > ARM( addeq pc, r12, r3 ) @ call cache function > THUMB( addeq r12, r3 ) > THUMB( moveq pc, r12 ) @ call cache function > @@ -1139,8 +1140,6 @@ call_cache_fn: adr r12, proc_types > */ > .align 5 > cache_off: mov r3, #12 @ cache_off function > - mov r10, r0 > - mov r11, r1 > b call_cache_fn > > __armv4_mpu_cache_off: > @@ -1173,22 +1172,21 @@ cache_off: mov r3, #12 @ cache_off function > mov pc, lr > > __armv7_mmu_cache_off: > - mrc p15, 0, r0, c1, c0 > + mrc p15, 0, r3, c1, c0 > #ifdef CONFIG_MMU > - bic r0, r0, #0x000d > + bic r3, r3, #0x000d > #else > - bic r0, r0, #0x000c > + bic r3, r3, #0x000c > #endif > - mcr p15, 0, r0, c1, c0 @ turn MMU and cache off > - mov r0, #0 > + mcr p15, 0, r3, c1, c0 @ turn MMU and cache off > + mov r3, #0 > #ifdef CONFIG_MMU > - mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB > + mcr p15, 0, r3, c8, c7, 0 @ invalidate whole TLB > #endif > - mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC > - mcr p15, 0, r0, c7, c10, 4 @ DSB > - mcr p15, 0, r0, c7, c5, 4 @ ISB > + mcr p15, 0, r3, c7, c5, 6 @ invalidate BTC > + mcr p15, 0, r3, c7, c10, 4 @ DSB > + mcr p15, 0, r3, c7, c5, 4 @ ISB > > - mov r0, r10 > b __armv7_mmu_cache_flush > > /* > @@ -1205,7 +1203,6 @@ cache_off: mov r3, #12 @ cache_off function > .align 5 > cache_clean_flush: > mov r3, #16 > - mov r11, r1 > b call_cache_fn > > __armv4_mpu_cache_flush: > @@ -1256,15 +1253,15 @@ cache_off: mov r3, #12 @ cache_off function > mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D > b iflush > hierarchical: > - dcache_line_size r1, r2 @ r1 := dcache min line size > - sub r2, r1, #1 @ r2 := line size mask > + dcache_line_size r11, r2 @ r11 := dcache min line size > + sub r2, r11, #1 @ r2 := line size mask > bic r0, r0, r2 @ round down start to line size > - sub r11, r11, #1 @ end address is exclusive > - bic r11, r11, r2 @ round down end to line size > -0: cmp r0, r11 @ finished? > + sub r1, r1, #1 @ end address is exclusive > + bic r1, r1, r2 @ round down end to line size > +0: cmp r0, r1 @ finished? > bgt iflush > mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA > - add r0, r0, r1 > + add r0, r0, r11 > b 0b > iflush: > mcr p15, 0, r10, c7, c10, 4 @ DSB > -- > 2.20.1 > > -- > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel