From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B40ACC433F5 for ; Mon, 30 May 2022 14:32:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g+1zrDoFVlSdb9TRfylhfYXP48Bqcw6l6ojGnWOpFdk=; b=xtw6IU8dH+GWSj RLn6qt8tKMjRhH19upQKDsQMOl9rBrClgQfGhYkOF7B9/eSzaU7jhtsv/bawK/2I2hQilMWsUcPqd 7jcO5oXmzLvMoJVdP20hAZCAdWyNnEToU7atDU0y1xkTu4oYdUGq3TpwzRLY3Cp9+gPFundCMCoR2 /WRGK6Rk0dn2aT9Q1F78iSTTfl0j0U3R5Yrk+GhFNK3Mx5WzobzMADT5q5M3GRMOUXK3NCyw/exoz GR2oOKf/PjPItT0JbxvRG3h66xw1bUl6L/zF6Gr6yBFjuJUwet6S25s42cLc/J0V2r7472/Mf2sZI Pz9EEpUN5SfMq54bzkvw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nvgQ1-007EHq-2C; Mon, 30 May 2022 14:30:53 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nvfpR-006vue-4N for linux-arm-kernel@lists.infradead.org; Mon, 30 May 2022 13:53:08 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8A3CEB80DE9 for ; Mon, 30 May 2022 13:53:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B75CC341C6 for ; Mon, 30 May 2022 13:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653918783; bh=MAX7wiH1XxyplvJYlh0+kplgAwx6qXFUDvATHGh08A4=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=DuEypzZccb0PLN/3B8rGnTR+J9Z164k7C50L3nvm7pTBT6MkFrfeMaXU+ImXTJ9AF bVRXyPEphWVyAaPYB2bgezXsH7UmwXlcr+hXbKoHXhZpWnOIDryLjDz8hvIO2Xlzvp pwN8aaHmM+LlX2Kv6/hr4QDPVNt/nhEyDmIyVy+Vffn50md6PUtbtzwnXwTTq4QpRP VROVhL9Llx7EnsOKpvEVHZWkV4Gum0cvJ+5IomhmUvv8Kl6uI4kAkJbIEla6xuy3/D knrSsqo6jbYaADoVRBO4huEqiM2UQTvxRDS00terKKizU+WuPrlEEIhZx4oZqvblIw TAjo7+TuczBNw== Received: by mail-oa1-f45.google.com with SMTP id 586e51a60fabf-f3381207a5so3152196fac.4 for ; Mon, 30 May 2022 06:53:03 -0700 (PDT) X-Gm-Message-State: AOAM530wL3lHdx4fWVNg4M7nmpbpGqV3WEy6ppJxld/u1pp7VdjOBzEY J8gZ63Sc3wl7103QtfhhJzxER4lx1PdIrgecdAM= X-Google-Smtp-Source: ABdhPJzdoo1sHFLLInFtt/hgXNHnvLFK6tnUHaPcCvCd7dg8vI8l0LUkCVEH8ofVkRXE/tkQtssOPOuGWKCysy8VVxw= X-Received: by 2002:a05:6870:eaa5:b0:da:b3f:2b45 with SMTP id s37-20020a056870eaa500b000da0b3f2b45mr10799698oap.228.1653918782369; Mon, 30 May 2022 06:53:02 -0700 (PDT) MIME-Version: 1.0 References: <20220530135057.1937286-1-sashal@kernel.org> <20220530135057.1937286-27-sashal@kernel.org> In-Reply-To: <20220530135057.1937286-27-sashal@kernel.org> From: Ard Biesheuvel Date: Mon, 30 May 2022 15:52:51 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH AUTOSEL 4.14 27/29] ARM: 9201/1: spectre-bhb: rely on linker to emit cross-section literal loads To: Sasha Levin Cc: Linux Kernel Mailing List , "# 3.4.x" , Russell King , Russell King , Linus Walleij , Nicolas Pitre , Arnd Bergmann , Linux ARM X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220530_065305_574948_8756FA56 X-CRM114-Status: GOOD ( 31.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org AUTONAK On Mon, 30 May 2022 at 15:52, Sasha Levin wrote: > > From: Ard Biesheuvel > > [ Upstream commit ad12c2f1587c6ec9b52ff226f438955bfae6ad89 ] > > The assembler does not permit 'LDR PC, ' when the symbol lives in a > different section, which is why we have been relying on rather fragile > open-coded arithmetic to load the address of the vector_swi routine into > the program counter using a single LDR instruction in the SWI slot in > the vector table. The literal was moved to a different section to in > commit 19accfd373847 ("ARM: move vector stubs") to ensure that the > vector stubs page does not need to be mapped readable for user space, > which is the case for the vector page itself, as it carries the kuser > helpers as well. > > So the cross-section literal load is open-coded, and this relies on the > address of vector_swi to be at the very start of the vector stubs page, > and we won't notice if we got it wrong until booting the kernel and see > it break. Fortunately, it was guaranteed to break, so this was fragile > but not problematic. > > Now that we have added two other variants of the vector table, we have 3 > occurrences of the same trick, and so the size of our ISA/compiler/CPU > validation space has tripled, in a way that may cause regressions to only > be observed once booting the image in question on a CPU that exercises a > particular vector table. > > So let's switch to true cross section references, and let the linker fix > them up like it fixes up all the other cross section references in the > vector page. > > Signed-off-by: Ard Biesheuvel > Signed-off-by: Russell King (Oracle) > Signed-off-by: Sasha Levin > --- > arch/arm/kernel/entry-armv.S | 22 +++++++++++++++------- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S > index e1b3c5c96560..0a9891df1ca4 100644 > --- a/arch/arm/kernel/entry-armv.S > +++ b/arch/arm/kernel/entry-armv.S > @@ -1102,10 +1102,15 @@ ENDPROC(vector_bhb_bpiall_\name) > .endm > > .section .stubs, "ax", %progbits > - @ This must be the first word > + @ These need to remain at the start of the section so that > + @ they are in range of the 'SWI' entries in the vector tables > + @ located 4k down. > +.L__vector_swi: > .word vector_swi > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > +.L__vector_bhb_loop8_swi: > .word vector_bhb_loop8_swi > +.L__vector_bhb_bpiall_swi: > .word vector_bhb_bpiall_swi > #endif > > @@ -1248,10 +1253,11 @@ vector_addrexcptn: > .globl vector_fiq > > .section .vectors, "ax", %progbits > -.L__vectors_start: > W(b) vector_rst > W(b) vector_und > - W(ldr) pc, .L__vectors_start + 0x1000 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) > + W(ldr) pc, . > W(b) vector_pabt > W(b) vector_dabt > W(b) vector_addrexcptn > @@ -1260,10 +1266,11 @@ vector_addrexcptn: > > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > .section .vectors.bhb.loop8, "ax", %progbits > -.L__vectors_bhb_loop8_start: > W(b) vector_rst > W(b) vector_bhb_loop8_und > - W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) > + W(ldr) pc, . > W(b) vector_bhb_loop8_pabt > W(b) vector_bhb_loop8_dabt > W(b) vector_addrexcptn > @@ -1271,10 +1278,11 @@ vector_addrexcptn: > W(b) vector_bhb_loop8_fiq > > .section .vectors.bhb.bpiall, "ax", %progbits > -.L__vectors_bhb_bpiall_start: > W(b) vector_rst > W(b) vector_bhb_bpiall_und > - W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi ) > + W(ldr) pc, . > W(b) vector_bhb_bpiall_pabt > W(b) vector_bhb_bpiall_dabt > W(b) vector_addrexcptn > -- > 2.35.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58DBDC433F5 for ; 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d=kernel.org; s=k20201202; t=1653918783; bh=MAX7wiH1XxyplvJYlh0+kplgAwx6qXFUDvATHGh08A4=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=DuEypzZccb0PLN/3B8rGnTR+J9Z164k7C50L3nvm7pTBT6MkFrfeMaXU+ImXTJ9AF bVRXyPEphWVyAaPYB2bgezXsH7UmwXlcr+hXbKoHXhZpWnOIDryLjDz8hvIO2Xlzvp pwN8aaHmM+LlX2Kv6/hr4QDPVNt/nhEyDmIyVy+Vffn50md6PUtbtzwnXwTTq4QpRP VROVhL9Llx7EnsOKpvEVHZWkV4Gum0cvJ+5IomhmUvv8Kl6uI4kAkJbIEla6xuy3/D knrSsqo6jbYaADoVRBO4huEqiM2UQTvxRDS00terKKizU+WuPrlEEIhZx4oZqvblIw TAjo7+TuczBNw== Received: by mail-oa1-f44.google.com with SMTP id 586e51a60fabf-e93bbb54f9so14363181fac.12; Mon, 30 May 2022 06:53:03 -0700 (PDT) X-Gm-Message-State: AOAM533whQR514x7Z/9EVR4dafsW+/n2OyhcIULbTyWNZ2vtxtYdx/Qj P4MQE688Zp/h9vW5mBgeu1ARoij9WkoAZFPnS9o= X-Google-Smtp-Source: ABdhPJzdoo1sHFLLInFtt/hgXNHnvLFK6tnUHaPcCvCd7dg8vI8l0LUkCVEH8ofVkRXE/tkQtssOPOuGWKCysy8VVxw= X-Received: by 2002:a05:6870:eaa5:b0:da:b3f:2b45 with SMTP id s37-20020a056870eaa500b000da0b3f2b45mr10799698oap.228.1653918782369; Mon, 30 May 2022 06:53:02 -0700 (PDT) MIME-Version: 1.0 References: <20220530135057.1937286-1-sashal@kernel.org> <20220530135057.1937286-27-sashal@kernel.org> In-Reply-To: <20220530135057.1937286-27-sashal@kernel.org> From: Ard Biesheuvel Date: Mon, 30 May 2022 15:52:51 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH AUTOSEL 4.14 27/29] ARM: 9201/1: spectre-bhb: rely on linker to emit cross-section literal loads To: Sasha Levin Cc: Linux Kernel Mailing List , "# 3.4.x" , Russell King , Russell King , Linus Walleij , Nicolas Pitre , Arnd Bergmann , Linux ARM Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AUTONAK On Mon, 30 May 2022 at 15:52, Sasha Levin wrote: > > From: Ard Biesheuvel > > [ Upstream commit ad12c2f1587c6ec9b52ff226f438955bfae6ad89 ] > > The assembler does not permit 'LDR PC, ' when the symbol lives in a > different section, which is why we have been relying on rather fragile > open-coded arithmetic to load the address of the vector_swi routine into > the program counter using a single LDR instruction in the SWI slot in > the vector table. The literal was moved to a different section to in > commit 19accfd373847 ("ARM: move vector stubs") to ensure that the > vector stubs page does not need to be mapped readable for user space, > which is the case for the vector page itself, as it carries the kuser > helpers as well. > > So the cross-section literal load is open-coded, and this relies on the > address of vector_swi to be at the very start of the vector stubs page, > and we won't notice if we got it wrong until booting the kernel and see > it break. Fortunately, it was guaranteed to break, so this was fragile > but not problematic. > > Now that we have added two other variants of the vector table, we have 3 > occurrences of the same trick, and so the size of our ISA/compiler/CPU > validation space has tripled, in a way that may cause regressions to only > be observed once booting the image in question on a CPU that exercises a > particular vector table. > > So let's switch to true cross section references, and let the linker fix > them up like it fixes up all the other cross section references in the > vector page. > > Signed-off-by: Ard Biesheuvel > Signed-off-by: Russell King (Oracle) > Signed-off-by: Sasha Levin > --- > arch/arm/kernel/entry-armv.S | 22 +++++++++++++++------- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S > index e1b3c5c96560..0a9891df1ca4 100644 > --- a/arch/arm/kernel/entry-armv.S > +++ b/arch/arm/kernel/entry-armv.S > @@ -1102,10 +1102,15 @@ ENDPROC(vector_bhb_bpiall_\name) > .endm > > .section .stubs, "ax", %progbits > - @ This must be the first word > + @ These need to remain at the start of the section so that > + @ they are in range of the 'SWI' entries in the vector tables > + @ located 4k down. > +.L__vector_swi: > .word vector_swi > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > +.L__vector_bhb_loop8_swi: > .word vector_bhb_loop8_swi > +.L__vector_bhb_bpiall_swi: > .word vector_bhb_bpiall_swi > #endif > > @@ -1248,10 +1253,11 @@ vector_addrexcptn: > .globl vector_fiq > > .section .vectors, "ax", %progbits > -.L__vectors_start: > W(b) vector_rst > W(b) vector_und > - W(ldr) pc, .L__vectors_start + 0x1000 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) > + W(ldr) pc, . > W(b) vector_pabt > W(b) vector_dabt > W(b) vector_addrexcptn > @@ -1260,10 +1266,11 @@ vector_addrexcptn: > > #ifdef CONFIG_HARDEN_BRANCH_HISTORY > .section .vectors.bhb.loop8, "ax", %progbits > -.L__vectors_bhb_loop8_start: > W(b) vector_rst > W(b) vector_bhb_loop8_und > - W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) > + W(ldr) pc, . > W(b) vector_bhb_loop8_pabt > W(b) vector_bhb_loop8_dabt > W(b) vector_addrexcptn > @@ -1271,10 +1278,11 @@ vector_addrexcptn: > W(b) vector_bhb_loop8_fiq > > .section .vectors.bhb.bpiall, "ax", %progbits > -.L__vectors_bhb_bpiall_start: > W(b) vector_rst > W(b) vector_bhb_bpiall_und > - W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008 > +ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) > +THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi ) > + W(ldr) pc, . > W(b) vector_bhb_bpiall_pabt > W(b) vector_bhb_bpiall_dabt > W(b) vector_addrexcptn > -- > 2.35.1 >