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From: Ard Biesheuvel <ardb@kernel.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,  Mark Brown <broonie@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] arm64: smccc: Save lr before calling __arm_smccc_sve_check()
Date: Tue, 20 Jul 2021 18:54:01 +0200	[thread overview]
Message-ID: <CAMj1kXH=rq36YP42-O5=72inWHqjcJ7=w5eod-DBmdmJceZJ1Q@mail.gmail.com> (raw)
In-Reply-To: <20210720163103.3836898-1-jean-philippe@linaro.org>

On Tue, 20 Jul 2021 at 18:37, Jean-Philippe Brucker
<jean-philippe@linaro.org> wrote:
>
> Commit cfa7ff959a78 ("arm64: smccc: Support SMCCC v1.3 SVE register
> saving hint") added a call to __arm_smccc_sve_check() which clobbers the
> lr (register x30), causing __arm_smccc_hvc() to return to itself and
> crash. Save lr on the stack before calling __arm_smccc_sve_check(), and
> adjust the offsets used to access stack parameters.
>
> Fixes: cfa7ff959a78 ("arm64: smccc: Support SMCCC v1.3 SVE register saving hint")
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

> ---
>
> Under QEMU TCG (-cpu max), PSCI calls now cause a BUG(), since the
> clobbered lr causes __arm_smccc_hvc() to return to the hvc instruction
> with invalid x0 parameter, which is treated as undefined instruction by
> TCG.
> ---
>  arch/arm64/kernel/smccc-call.S | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S
> index d3d37f932b97..c16679eec7af 100644
> --- a/arch/arm64/kernel/smccc-call.S
> +++ b/arch/arm64/kernel/smccc-call.S
> @@ -32,20 +32,22 @@ SYM_FUNC_END(__arm_smccc_sve_check)
>  EXPORT_SYMBOL(__arm_smccc_sve_check)
>
>         .macro SMCCC instr
> +       stp     x29, x30, [sp, #-16]!

Please add a

mov x29, sp

here to create a proper stack frame

With that

Acked-by: Ard Biesheuvel <ardb@kernel.org>


>  alternative_if ARM64_SVE
>         bl      __arm_smccc_sve_check
>  alternative_else_nop_endif
>         \instr  #0
> -       ldr     x4, [sp]
> +       ldr     x4, [sp, #16]
>         stp     x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
>         stp     x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
> -       ldr     x4, [sp, #8]
> +       ldr     x4, [sp, #24]
>         cbz     x4, 1f /* no quirk structure */
>         ldr     x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
>         cmp     x9, #ARM_SMCCC_QUIRK_QCOM_A6
>         b.ne    1f
>         str     x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
> -1:     ret
> +1:     ldp     x29, x30, [sp], #16
> +       ret
>         .endm
>
>  /*
> --
> 2.32.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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  reply	other threads:[~2021-07-20 16:56 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-20 16:31 [PATCH] arm64: smccc: Save lr before calling __arm_smccc_sve_check() Jean-Philippe Brucker
2021-07-20 16:54 ` Ard Biesheuvel [this message]
2021-07-20 20:32 ` Mark Brown

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