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Mon, 24 May 2021 02:42:04 -0700 (PDT) MIME-Version: 1.0 References: <20210524083001.2586635-1-tabba@google.com> <20210524083001.2586635-5-tabba@google.com> In-Reply-To: From: Ard Biesheuvel Date: Mon, 24 May 2021 11:41:53 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range To: Fuad Tabba Cc: Linux ARM , Will Deacon , Catalin Marinas , Mark Rutland , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Robin Murphy X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_024205_868155_AEFD48A6 X-CRM114-Status: GOOD ( 23.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 24 May 2021 at 11:20, Fuad Tabba wrote: > > Hi Ard, > > > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > > > index 2d881f34dd9d..7c54bcbf5a36 100644 > > > --- a/arch/arm64/mm/cache.S > > > +++ b/arch/arm64/mm/cache.S > > > @@ -14,6 +14,34 @@ > > > #include > > > #include > > > > > > +/* > > > + * __flush_cache_range(start,end) [fixup] > > > + * > > > + * Ensure that the I and D caches are coherent within specified region. > > > + * This is typically used when code has been written to a memory region, > > > + * and will be executed. > > > + * > > > + * - start - virtual start address of region > > > + * - end - virtual end address of region > > > + * - fixup - optional label to branch to on user fault > > > + */ > > > +.macro __flush_cache_range, fixup > > > +alternative_if ARM64_HAS_CACHE_IDC > > > + dsb ishst > > > > Should this perhaps be dsb ish? IIUC, ishst does not synchronize on > > completion of cache maintenance, and while that is implicit on this > > code path, I'd still assume it needs to complete before carrying on. > > Or does IDC not require this? > > I'm not sure; ishst in this patch is unchanged (just moved to the > macro). Reading the Arm ARM (B2-143) I think that ishst is correct: > > """ > CTR_EL0.{DIC, IDC} == {0, 1} > > The write is complete for the shareability domain. Subsequently the > location has been invalidated to the Point of unification (PoU) from > the instruction cache, and that invalidation is complete for the > shareability domain. > > CTR_EL0.{DIC, IDC} == {1, 1} > > The write is complete for the shareability domain. > """ > > Does my interpretation sound right to you? > Thanks for digging that up. So IDC does guarantee that completing the store is sufficient for the I-side to observe it, so I think your interpretation is correct. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel