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s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=i+if+LTW7LaDImwlr7+eQ14QH9rmxrDj9p23CUU4mSw=; b=kzDiuR00Z83Ej/LbupfzJAOfQ7Qw/i96k8h82S/ZArJUSYE7Mq4Goq+yWXiEk0QIyA OkrUNKGCr6ed/SBgE7La6hzQxxq2N4ujbnj1gam4ZtWTbBa1+hDGKS5t4aem5MzuWumR QxRJZcyPivVHjvjNsh4b4d/ZDwoImqmYpazZA2RLdmZtYmgq65/zHGqnlQGbupriNnuu Y7gPfG6X6eP8+TyoJlp/zTFvdmrd7g9vB70bDP3d4wcAFG9OysiSqIIEhnv2liaBtB9t /9ZG8J3gf1QC2vhyHBX0QqNqnXSFtd1cQVjA4/YbHGGsCg/WobwW6RVhnUgo1XkP0yc7 LqGg== X-Gm-Message-State: AOAM531jCSp4Wcc/YVgrxl+j+eAYcGYDSsNkC1sHY8ZIT+YpdXvoxCxw JcBQuen0dNrIuzRjfIG3BGmqmoKTZxOWZUpwOaMRuQ== X-Google-Smtp-Source: ABdhPJyPrL7mY/AX35E+Wn10FZreuPO5pRpKlTdpi+4O9jmdE95cD0AyMrYJ9t5YeqdlIsuIkuZ3yV4zP1ui6H3sBCY= X-Received: by 2002:a6b:3e04:: with SMTP id l4mr1060783ioa.66.1625251184222; Fri, 02 Jul 2021 11:39:44 -0700 (PDT) MIME-Version: 1.0 References: <20210702031922.1291398-1-pcc@google.com> <20210702174450.GC685@arm.com> In-Reply-To: <20210702174450.GC685@arm.com> From: Peter Collingbourne Date: Fri, 2 Jul 2021 11:39:33 -0700 Message-ID: Subject: Re: [PATCH] arm64: mte: switch GCR_EL1 on task switch rather than entry/exit To: Catalin Marinas Cc: Vincenzo Frascino , Will Deacon , Andrey Konovalov , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , Linux ARM X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210702_113947_510585_FA00E4EB X-CRM114-Status: GOOD ( 18.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 2, 2021 at 10:44 AM Catalin Marinas wrote: > > On Thu, Jul 01, 2021 at 08:19:22PM -0700, Peter Collingbourne wrote: > > Accessing GCR_EL1 and issuing an ISB can be expensive on some > > microarchitectures. To avoid taking this performance hit on every > > kernel entry/exit, switch GCR_EL1 on task switch rather than > > entry/exit. > > Is it the ISB that's causing issues or the MRS/MSR as well? I think we > can avoid the ISB when PtrAuth is enabled by shuffling the entry code a > bit. We can also simplify the mte_set_gcr macro to avoid an MRS. This was the first thing that I tried on our hardware: diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 7312eafec946..8699ab28a924 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -204,7 +204,6 @@ alternative_else_nop_endif ldr_l \tmp, gcr_kernel_excl mte_set_gcr \tmp, \tmp2 - isb 1: #endif .endm @@ -277,13 +276,13 @@ alternative_if ARM64_HAS_ADDRESS_AUTH orr x0, x0, SCTLR_ELx_ENIA msr sctlr_el1, x0 2: - isb alternative_else_nop_endif #endif apply_ssbd 1, x22, x23 mte_set_kernel_gcr x22, x23 + isb scs_load tsk, x20 .else However, on most of the cores this led to only around half of the performance improvement of the patch that I sent. Which is somewhat surprising, but it is what it is. But I would like to get IRG out of the kernel (at least in production kernels) for other reasons. I would at some point like to add a deterministic IRG mode (to support record/replay debugging). This will require setting RRND=0 and a per-task RGSR. If we then allow IRG in the kernel we would need to manually switch RGSR here as well. Peter _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel