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From: Max Filippov <jcmvbkbc@gmail.com>
Date: Thu, 26 Apr 2018 11:55:32 -0700
Message-ID: <CAMo8BfKJwZOCaQrSCnFMVNy=L8Z0yo7sAw3q5Sfaof-ko_+NjQ@mail.gmail.com>
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Subject: Re: [Qemu-devel] [RFC PATCH] hw/core: expand description of
 null-machine
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To: Thomas Huth <thuth@redhat.com>
Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Marcel Apfelbaum <marcel@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, qemu-devel <qemu-devel@nongnu.org>, Eduardo Habkost <ehabkost@redhat.com>

On Thu, Apr 26, 2018 at 11:18 AM, Thomas Huth <thuth@redhat.com> wrote:
> On 26.04.2018 18:09, Alex Benn=C3=A9e wrote:
>> Thomas Huth <thuth@redhat.com> writes:
>>> Actually, with certain CPUs, you can really use the "none" machine as a
>>> pure instruction set testing system. For example, on m68k, there used t=
o
>>> be an explicit "dummy" machine for this job, and we removed it in favou=
r
>>> of the "none" machine:
>>>
>>> https://git.qemu.org/?p=3Dqemu.git;a=3Dcommitdiff;h=3D22f2dbe7eaf3e12e3=
8c9c210
>>
>> Ahh OK. Do you know what other CPUs can be used in this way?
>
> I think it should be possible with at least all the boards that have a
> "sim" machine, e.g. xtensa, mips, moxie and openrisc.

xtensa sim machine is a bit more than just instruction simulator:
it instantiates CPU-configuration-specific local memories. It is meant
to be compatible with Xtensa ISS from Xtensa development tools.

--=20
Thanks.
-- Max