From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C69EC4338F for ; Fri, 23 Jul 2021 07:31:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07E6860E8B for ; Fri, 23 Jul 2021 07:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229774AbhGWGue (ORCPT ); Fri, 23 Jul 2021 02:50:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229733AbhGWGud (ORCPT ); Fri, 23 Jul 2021 02:50:33 -0400 Received: from mail-yb1-xb29.google.com (mail-yb1-xb29.google.com [IPv6:2607:f8b0:4864:20::b29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF666C061575 for ; Fri, 23 Jul 2021 00:31:07 -0700 (PDT) Received: by mail-yb1-xb29.google.com with SMTP id s19so941443ybc.6 for ; Fri, 23 Jul 2021 00:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vs+we/6ft1FfVa0CVz20fRewulUcTgapCBk4PsMDMMQ=; b=JPyoG4tDLazDPsS8Y3oVxlDJm75zO3sr5Mwj9G2MnrcoE/tXE6m8Q7IDz7QI/HrG18 xlTRSLavT1GWOuRuJSRa2gKNvB9Z25aSlfeFzmf4rtlDTcVQrSqDVdbuiz1aFt9AbmVS Bn8n8SkRdYMai4NwvEI2Suhn5IvGbTMAXHcMmlN6kBJA2EWAbj7uqaOsdhx5HR6dXh8E Qu1hiLp388RZyk+2SNzk0qHrlu7vQ9ohNOQXse3g8P03+XwbTLKU0GKBYXQl3hnFj5QG 4FyAaDXc/oappirdBhHoW7wA1+nwd8NCic04Fu6HtgJ0cfr4lCEuzvZxjEWRXAJEZ9Pv uHGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vs+we/6ft1FfVa0CVz20fRewulUcTgapCBk4PsMDMMQ=; b=VTFl9RCGKADv7ZfVstCwukB+3Wng13NVSjKNUMY1KH3AJAJ56502UW4SYCR82L9JS8 S1FgtqSvjtVp8CIhAVWOye0iDUbZLnunoT021N62U42xhOGIzNSOgcN9IAQsZJDCTi/k 3+3AtKJuyiSJE5CcrBOdFyEQK7zaqa0XkifGFFKGFr9i6EGLP0MWlRRPthyCqb7rClAE NQG64aPE1SpBe/nd+YOmYctNsleaT4MNiVh8QpBMNOwpXG176ctd4pGPP0UTyQ9l3b8v EMkGeI1YRx+fv6yotBZ8taEwcHqrxhsJp1qMbu4aFHLVVkJK/xTN4DNEV1U1YENk+Vjd vK7Q== X-Gm-Message-State: AOAM530O2kFYAsMRAFlxOnLcNLkyOVTnuTghGgr5T3+DAv2xR6jHPMLV PzmzYIKBsoFF6HEIgFPEa8Ujw3gW3MjwwW4USmAR4w== X-Google-Smtp-Source: ABdhPJwg0akw1mzLE5SRir9S3txrzipyiauGM7ybFw0aTjvqg6GRL6JrZTEfDza78OmWm3R7qONfl5YzUx+jnBc5bxE= X-Received: by 2002:a25:487:: with SMTP id 129mr5006427ybe.0.1627025466848; Fri, 23 Jul 2021 00:31:06 -0700 (PDT) MIME-Version: 1.0 References: <20210712100317.23298-1-steven_lee@aspeedtech.com> <20210723031615.GA10457@aspeedtech.com> In-Reply-To: <20210723031615.GA10457@aspeedtech.com> From: Bartosz Golaszewski Date: Fri, 23 Jul 2021 09:30:56 +0200 Message-ID: Subject: Re: [PATCH v6 0/9] ASPEED sgpio driver enhancement. To: Steven Lee , Joel Stanley , Andrew Jeffery Cc: Linus Walleij , Rob Herring , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongwei Zhang , Ryan Chen , Billy Tsai Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, Jul 23, 2021 at 5:16 AM Steven Lee wrote: > > The 07/21/2021 21:27, Bartosz Golaszewski wrote: > > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee wrote: > > > > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > > supports up to 80 pins. > > > In the current driver design, the max number of sgpio pins is hardcoded > > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > > contains the following enhancement: > > > - Convert txt dt-bindings to yaml. > > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > > - Support muiltiple SGPIO master interfaces. > > > - Support up to 128 pins by dts ngpios property. > > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > > > MAX_NR_HW_SGPIO as GPIO output pin base. > > > - Support wdt reset tolerance. > > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > > irq_chip data. > > > - Replace all of_*() APIs with device_*(). > > > > > > Changes from v5: > > > * Squash v5 patch-05 and patch-06 to one patch. > > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > > > input/output pin base are determined by ngpios. > > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > > > pin order is as follows: > > > Input: > > > 0 1 2 3 ... 9 > > > Output: > > > 80 81 82 ... 89 > > > > > > With the new design, pin order is changed as follows: > > > Input: > > > 0 2 4 6 ... 18(ngpios * 2 - 2) > > > Output: > > > 1 3 5 7 ... 19(ngpios * 2 - 1) > > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > > > ast2600-sgpiom. > > > * Fix coding style issues. > > > > > > Changes from v4: > > > * Remove ngpios from dtsi > > > * Add ast2400 and ast2500 platform data. > > > * Remove unused macros. > > > * Add ngpios check in a separate patch. > > > * Fix coding style issues. > > > > > > Changes from v3: > > > * Split dt-bindings patch to 2 patches > > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > > > * Correct the typo in commit messages. > > > * Fix coding style issues. > > > * Replace all of_*() APIs with device_*(). > > > > > > Changes from v2: > > > * Remove maximum/minimum of ngpios from bindings. > > > * Remove max-ngpios from bindings and dtsi. > > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > > > driver. > > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > > > number of available gpio pins are different. > > > * Modify functions to pass aspeed_sgpio struct instead of passing > > > max_ngpios. > > > * Split sgpio driver patch to 3 patches > > > > > > Changes from v1: > > > * Fix yaml format issues. > > > * Fix issues reported by kernel test robot. > > > > > > Please help to review. > > > > > > Thanks, > > > Steven > > > > > > Steven Lee (9): > > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > > > ARM: dts: aspeed-g6: Add SGPIO node. > > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > > > gpio: gpio-aspeed-sgpio: Add set_config function > > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > > > gpio: gpio-aspeed-sgpio: Use generic device property APIs > > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > > > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > > > 5 files changed, 215 insertions(+), 115 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > > > > > -- > > > 2.17.1 > > > > > > > The series looks good to me. Can the DTS and GPIO patches go into > > v5.15 separately? > > > > Hi Bart, > > Thanks for the review. > Shall we do anything to make the patches go into v5.15 or wait for picking-up? > > Steven > > > Bart It's more of a question to the relevant SoC maintainers. Joel, Andrew: can I take the GPIO patches through the GPIO tree and you'll take the ARM patches separately into v5.15? Bartosz From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDE4AC4338F for ; Fri, 23 Jul 2021 07:32:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9F02060E8E for ; Fri, 23 Jul 2021 07:32:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9F02060E8E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e+SgZM98Nbuib+mZEbpQtmK0LdF+8Hovr7BQI+FKixU=; b=4KL22y5EWbttX+ QMI6QjrGWYw5yrIiWyOtz5nTCzBWeJnUMEhOk+dLLQk+TqtiEAZSlLuhL3jGo/VvFc3r3bMI/8AZN WzcQ8ddpza1+0wcn8iPB2S+bfAAbqaB75UYgxqXeg9NB+Df6C+MolyD9WwJl7AyKwuxkV+Hl4EqSF l4JyuTi9onghZHM4USuQEzlWZJw5ErziMI5wcrvgSxahBVABMxWRziw9GVDrHVmxmhZJJ4zaxPfs8 pycW1ogP8eAa06aDPJnVwp9zbE0yw7STN4Uv+Jpes1vq8KtLSrmr0mQeD49X1FwBUovZ9fXEBhYg+ MViLmakVkhFI75PpVy3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6peL-003hES-Ox; Fri, 23 Jul 2021 07:31:13 +0000 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6peH-003hDE-28 for linux-arm-kernel@lists.infradead.org; Fri, 23 Jul 2021 07:31:11 +0000 Received: by mail-yb1-xb32.google.com with SMTP id f26so961973ybj.5 for ; Fri, 23 Jul 2021 00:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vs+we/6ft1FfVa0CVz20fRewulUcTgapCBk4PsMDMMQ=; b=JPyoG4tDLazDPsS8Y3oVxlDJm75zO3sr5Mwj9G2MnrcoE/tXE6m8Q7IDz7QI/HrG18 xlTRSLavT1GWOuRuJSRa2gKNvB9Z25aSlfeFzmf4rtlDTcVQrSqDVdbuiz1aFt9AbmVS Bn8n8SkRdYMai4NwvEI2Suhn5IvGbTMAXHcMmlN6kBJA2EWAbj7uqaOsdhx5HR6dXh8E Qu1hiLp388RZyk+2SNzk0qHrlu7vQ9ohNOQXse3g8P03+XwbTLKU0GKBYXQl3hnFj5QG 4FyAaDXc/oappirdBhHoW7wA1+nwd8NCic04Fu6HtgJ0cfr4lCEuzvZxjEWRXAJEZ9Pv uHGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vs+we/6ft1FfVa0CVz20fRewulUcTgapCBk4PsMDMMQ=; b=aTBi2P6w/btC9rCeVPRdZc7ROkb0Oc66J3VmlVMci4rMYG8oldk0xRiv0oLZrjnlmX zQT+paACqsI9wEx60Qv9RZU4k287kqKlaMZfX7U+h7K8NKXqazGD3f1XQHl/EJ3TU1Mu ng9d8rCC30smVWxbMn1+8IrP+aMmQBUfHEh6w1nYNxWJ14ZV6vrGoXcinHc2ZsEQ9aG6 Tqc2qKsMC0ztdlL7zjIguOh5WUl1J4W4hGsSKF4EM2ZJihR7qWWD3K8CfyuDx0gpytoA RmgSqcT8HlVE1vg5ZcF9b9dkGf1Q0uZN6SG8XBTPDKm0GsD0m4af9WLTGXo+1/1PjIkr qQcQ== X-Gm-Message-State: AOAM531ABjVYMjHbaKR1Dgr0V+MJD9F6OUczdbKKHEuoM8wBDe+gyGG1 hC8ja8o+fe/p+TRK+mFV4dP1sqDQwfadMYFIxJGOXA== X-Google-Smtp-Source: ABdhPJwg0akw1mzLE5SRir9S3txrzipyiauGM7ybFw0aTjvqg6GRL6JrZTEfDza78OmWm3R7qONfl5YzUx+jnBc5bxE= X-Received: by 2002:a25:487:: with SMTP id 129mr5006427ybe.0.1627025466848; Fri, 23 Jul 2021 00:31:06 -0700 (PDT) MIME-Version: 1.0 References: <20210712100317.23298-1-steven_lee@aspeedtech.com> <20210723031615.GA10457@aspeedtech.com> In-Reply-To: <20210723031615.GA10457@aspeedtech.com> From: Bartosz Golaszewski Date: Fri, 23 Jul 2021 09:30:56 +0200 Message-ID: Subject: Re: [PATCH v6 0/9] ASPEED sgpio driver enhancement. To: Steven Lee , Joel Stanley , Andrew Jeffery Cc: Linus Walleij , Rob Herring , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongwei Zhang , Ryan Chen , Billy Tsai X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210723_003109_213280_BD237F8C X-CRM114-Status: GOOD ( 36.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 23, 2021 at 5:16 AM Steven Lee wrote: > > The 07/21/2021 21:27, Bartosz Golaszewski wrote: > > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee wrote: > > > > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > > supports up to 80 pins. > > > In the current driver design, the max number of sgpio pins is hardcoded > > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > > contains the following enhancement: > > > - Convert txt dt-bindings to yaml. > > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > > - Support muiltiple SGPIO master interfaces. > > > - Support up to 128 pins by dts ngpios property. > > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and > > > MAX_NR_HW_SGPIO as GPIO output pin base. > > > - Support wdt reset tolerance. > > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > > irq_chip data. > > > - Replace all of_*() APIs with device_*(). > > > > > > Changes from v5: > > > * Squash v5 patch-05 and patch-06 to one patch. > > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio > > > input/output pin base are determined by ngpios. > > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original > > > pin order is as follows: > > > Input: > > > 0 1 2 3 ... 9 > > > Output: > > > 80 81 82 ... 89 > > > > > > With the new design, pin order is changed as follows: > > > Input: > > > 0 2 4 6 ... 18(ngpios * 2 - 2) > > > Output: > > > 1 3 5 7 ... 19(ngpios * 2 - 1) > > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by > > > ast2600-sgpiom. > > > * Fix coding style issues. > > > > > > Changes from v4: > > > * Remove ngpios from dtsi > > > * Add ast2400 and ast2500 platform data. > > > * Remove unused macros. > > > * Add ngpios check in a separate patch. > > > * Fix coding style issues. > > > > > > Changes from v3: > > > * Split dt-bindings patch to 2 patches > > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128 > > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80 > > > * Correct the typo in commit messages. > > > * Fix coding style issues. > > > * Replace all of_*() APIs with device_*(). > > > > > > Changes from v2: > > > * Remove maximum/minimum of ngpios from bindings. > > > * Remove max-ngpios from bindings and dtsi. > > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and > > > driver. > > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max > > > number of available gpio pins are different. > > > * Modify functions to pass aspeed_sgpio struct instead of passing > > > max_ngpios. > > > * Split sgpio driver patch to 3 patches > > > > > > Changes from v1: > > > * Fix yaml format issues. > > > * Fix issues reported by kernel test robot. > > > > > > Please help to review. > > > > > > Thanks, > > > Steven > > > > > > Steven Lee (9): > > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. > > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio > > > ARM: dts: aspeed-g6: Add SGPIO node. > > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support > > > gpio: gpio-aspeed-sgpio: Add set_config function > > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct > > > gpio: gpio-aspeed-sgpio: Use generic device property APIs > > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8. > > > > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++ > > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ----- > > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++ > > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++------- > > > 5 files changed, 215 insertions(+), 115 deletions(-) > > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > > > > > -- > > > 2.17.1 > > > > > > > The series looks good to me. Can the DTS and GPIO patches go into > > v5.15 separately? > > > > Hi Bart, > > Thanks for the review. > Shall we do anything to make the patches go into v5.15 or wait for picking-up? > > Steven > > > Bart It's more of a question to the relevant SoC maintainers. Joel, Andrew: can I take the GPIO patches through the GPIO tree and you'll take the ARM patches separately into v5.15? Bartosz _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel