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Fri, 08 Oct 2021 05:36:50 -0700 (PDT) MIME-Version: 1.0 References: <20210914032231.273509-1-marex@denx.de> <20210914174230.ioalzc45yq37krot@ti.com> <47ef9ee8-81f7-da64-bd90-7c282cae354c@denx.de> <20210915082821.gofegwxuagrfee5i@ti.com> In-Reply-To: From: Jagan Teki Date: Fri, 8 Oct 2021 18:06:39 +0530 Message-ID: Subject: Re: [PATCH] mtd: cqspi: Wait for transfer completion To: Marek Vasut , Pratyush Yadav Cc: U-Boot-Denx , Vignesh R Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote: > > On 9/15/21 10:28 AM, Pratyush Yadav wrote: > > On 14/09/21 08:22PM, Marek Vasut wrote: > >> On 9/14/21 7:42 PM, Pratyush Yadav wrote: > >>> On 14/09/21 05:22AM, Marek Vasut wrote: > >>>> Wait for the read/write transfer finish bit get actually cleared, > >>>> this does not happen immediately on at least SoCFPGA Gen5. > >>>> > >>>> Signed-off-by: Marek Vasut > >>>> Cc: Jagan Teki > >>>> Cc: Vignesh R > >>>> Cc: Pratyush Yadav > >>>> --- > >>>> drivers/spi/cadence_qspi_apb.c | 17 +++++++++++++++++ > >>>> 1 file changed, 17 insertions(+) > >>>> > >>>> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > >>>> index 429ee335db6..2cdf4c9c9f8 100644 > >>>> --- a/drivers/spi/cadence_qspi_apb.c > >>>> +++ b/drivers/spi/cadence_qspi_apb.c > >>>> @@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, > >>>> writel(CQSPI_REG_INDIRECTRD_DONE, > >>>> plat->regbase + CQSPI_REG_INDIRECTRD); > >>>> + /* Check indirect done status */ > >>>> + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, > >>>> + CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); > >>>> + if (ret) { > >>>> + printf("Indirect read clear completion error (%i)\n", ret); > >>>> + goto failrd; > >>>> + } > >>>> + > >>> > >>> Huh, this is strange. I would expect the bit to clear immediately since > >>> it doesn't really do any operation on the flash. How long does it > >>> usually take to clear? If you don't wait for it to clear does anything > >>> break? > >> > >> Often it does clear immediately, but there were a few odd cases where it did > >> not happen right away, in which case I had transfer corruption. > > > > By "transfer corruption" do you mean the current transfer gets corrupted > > or the next one? > > > > We get here _after_ the transfer is completed and this bit should have > > little to do with the data received. If the current transfer fails then > > I suspect something else might be going wrong the this is just a symptom > > of the problem. > > As far as I recall, the problem was triggered when using UBI on the SPI > NOR, so that could very well be the next transfer. Any further decisions here? shall I take it or v2? Jagan.