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* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
@ 2019-10-03 12:59 Marek Vasut
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
                   ` (3 more replies)
  0 siblings, 4 replies; 16+ messages in thread
From: Marek Vasut @ 2019-10-03 12:59 UTC (permalink / raw)
  To: u-boot

Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
V2: Use non-DM watchdog in SPL on S10
---
 configs/socfpga_stratix10_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig     | 1 +
 drivers/watchdog/Kconfig                  | 7 +++++++
 include/configs/socfpga_common.h          | 3 ---
 include/configs/socfpga_stratix10_socdk.h | 6 ++++--
 scripts/config_whitelist.txt              | 1 -
 6 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index ad83f50032..462082b67b 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 96f806ab5f..03c43fa8b9 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index a66a9bcbe2..6fd9b0a177 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -36,6 +36,13 @@ config ULP_WATCHDOG
 	help
 	  Say Y here to enable i.MX7ULP watchdog driver.
 
+config DESIGNWARE_WATCHDOG
+	bool "Designware watchdog timer support"
+	select HW_WATCHDOG
+	help
+	   Enable this to support Designware Watchdog Timer IP, present e.g.
+	   on Altera SoCFPGA SoCs.
+
 config WDT
 	bool "Enable driver model for watchdog timer drivers"
 	depends on DM
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b11fe021a7..32b9131be0 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -104,12 +104,9 @@
 /*
  * L4 Watchdog
  */
-#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
-#endif
 
 /*
  * MMC Driver
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 7b55dd14da..353e08f982 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -162,14 +162,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
+#else
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_DESIGNWARE_WATCHDOG
+#endif
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
 #endif
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS	3000
-#endif
 
 /*
  * SPL memory layout
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b18eab1707..839eda8c0f 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR
 CONFIG_DEF_HWCONFIG
 CONFIG_DELAY_ENVIRONMENT
 CONFIG_DESIGNWARE_ETH
-CONFIG_DESIGNWARE_WATCHDOG
 CONFIG_DEVELOP
 CONFIG_DEVICE_TREE_LIST
 CONFIG_DFU_ALT
-- 
2.23.0

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-10-03 12:59 [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Marek Vasut
@ 2019-10-03 12:59 ` Marek Vasut
  2019-10-04  9:26   ` Ley Foon Tan
                     ` (2 more replies)
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 3/3] watchdog: designware: Optionally fetch clock from DT Marek Vasut
                   ` (2 subsequent siblings)
  3 siblings, 3 replies; 16+ messages in thread
From: Marek Vasut @ 2019-10-03 12:59 UTC (permalink / raw)
  To: u-boot

Convert the designware watchdog timer driver to DM and add DT probing
support. Perform minor coding style clean up, like drop superfluous
braces. There ought to be no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
V2: - Support both DM and non-DM probing
    - Fix watchdog stop handling by setting CR bit
---
 configs/socfpga_stratix10_defconfig       |   2 +
 configs/socfpga_vining_fpga_defconfig     |   1 +
 drivers/watchdog/Kconfig                  |   2 +-
 drivers/watchdog/designware_wdt.c         | 122 ++++++++++++++++++----
 include/configs/socfpga_stratix10_socdk.h |   1 +
 5 files changed, 104 insertions(+), 24 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 462082b67b..752fa545bd 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -57,3 +57,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
 CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 03c43fa8b9..def7a3eca7 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_WDT=y
 CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6fd9b0a177..bfb91af947 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -38,7 +38,7 @@ config ULP_WATCHDOG
 
 config DESIGNWARE_WATCHDOG
 	bool "Designware watchdog timer support"
-	select HW_WATCHDOG
+	select HW_WATCHDOG if !WDT
 	help
 	   Enable this to support Designware Watchdog Timer IP, present e.g.
 	   on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index c668567c66..a7b735979a 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -4,7 +4,8 @@
  */
 
 #include <common.h>
-#include <watchdog.h>
+#include <dm.h>
+#include <wdt.h>
 #include <asm/io.h>
 #include <asm/utils.h>
 
@@ -17,46 +18,51 @@
 #define DW_WDT_CR_RMOD_VAL	0x00
 #define DW_WDT_CRR_RESTART_VAL	0x76
 
+struct designware_wdt_priv {
+	void __iomem	*base;
+};
+
 /*
  * Set the watchdog time interval.
  * Counter is 32 bit.
  */
-static int designware_wdt_settimeout(unsigned int timeout)
+static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
+				     unsigned int timeout)
 {
 	signed int i;
 
 	/* calculate the timeout range value */
-	i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
-	if (i > 15)
-		i = 15;
-	if (i < 0)
-		i = 0;
+	i = log_2_n_round_up(timeout * clk_khz) - 16;
+	i = clamp(i, 0, 15);
+
+	writel(i | (i << 4), base + DW_WDT_TORR);
 
-	writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
 	return 0;
 }
 
-static void designware_wdt_enable(void)
+static void designware_wdt_enable(void __iomem *base)
 {
-	writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
-	      (0x1 << DW_WDT_CR_EN_OFFSET)),
-	      (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+	writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+		BIT(DW_WDT_CR_EN_OFFSET),
+		base + DW_WDT_CR);
 }
 
-static unsigned int designware_wdt_is_enabled(void)
+static unsigned int designware_wdt_is_enabled(void __iomem *base)
 {
-	unsigned long val;
-	val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
-	return val & 0x1;
+	return readl(base + DW_WDT_CR) & BIT(0);
 }
 
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
+static void designware_wdt_reset_common(void __iomem *base)
 {
-	if (designware_wdt_is_enabled())
+	if (designware_wdt_is_enabled(base))
 		/* restart the watchdog counter */
-		writel(DW_WDT_CRR_RESTART_VAL,
-		       (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+		writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
+}
+
+#if !CONFIG_IS_ENABLED(WDT)
+void hw_watchdog_reset(void)
+{
+	designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
 }
 
 void hw_watchdog_init(void)
@@ -64,10 +70,80 @@ void hw_watchdog_init(void)
 	/* reset to disable the watchdog */
 	hw_watchdog_reset();
 	/* set timer in miliseconds */
-	designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
+	designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
+				  CONFIG_DW_WDT_CLOCK_KHZ,
+				  CONFIG_WATCHDOG_TIMEOUT_MSECS);
 	/* enable the watchdog */
-	designware_wdt_enable();
+	designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
 	/* reset the watchdog */
 	hw_watchdog_reset();
 }
+#else
+static int designware_wdt_reset(struct udevice *dev)
+{
+	struct designware_wdt_priv *priv = dev_get_priv(dev);
+
+	designware_wdt_reset_common(priv->base);
+
+	return 0;
+}
+
+static int designware_wdt_stop(struct udevice *dev)
+{
+	struct designware_wdt_priv *priv = dev_get_priv(dev);
+
+	designware_wdt_reset(dev);
+	writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
+		priv->base + DW_WDT_CR);
+
+	return 0;
+}
+
+static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct designware_wdt_priv *priv = dev_get_priv(dev);
+
+	designware_wdt_stop(dev);
+
+	/* set timer in miliseconds */
+	designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
+
+	designware_wdt_enable(priv->base);
+
+	/* reset the watchdog */
+	return designware_wdt_reset(dev);
+}
+
+static int designware_wdt_probe(struct udevice *dev)
+{
+	struct designware_wdt_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	/* reset to disable the watchdog */
+	return designware_wdt_stop(dev);
+}
+
+static const struct wdt_ops designware_wdt_ops = {
+	.start = designware_wdt_start,
+	.reset = designware_wdt_reset,
+	.stop = designware_wdt_stop,
+};
+
+static const struct udevice_id designware_wdt_ids[] = {
+	{ .compatible = "snps,dw-wdt"},
+	{}
+};
+
+U_BOOT_DRIVER(designware_wdt) = {
+	.name = "designware_wdt",
+	.id = UCLASS_WDT,
+	.of_match = designware_wdt_ids,
+	.priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
+	.probe = designware_wdt_probe,
+	.ops = &designware_wdt_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
 #endif
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 353e08f982..0c0c27000a 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -161,6 +161,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * L4 Watchdog
  */
 #ifdef CONFIG_SPL_BUILD
+#undef CONFIG_WATCHDOG
 #define CONFIG_HW_WATCHDOG
 #else
 #undef CONFIG_HW_WATCHDOG
-- 
2.23.0

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] watchdog: designware: Optionally fetch clock from DT
  2019-10-03 12:59 [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Marek Vasut
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
@ 2019-10-03 12:59 ` Marek Vasut
  2019-10-04  8:59 ` [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Ley Foon Tan
  2019-11-07 19:27 ` Simon Goldschmidt
  3 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2019-10-03 12:59 UTC (permalink / raw)
  To: u-boot

Add optional support for fetching watchdog clock rate from DT.
This is optional as not all platforms using DW WDT support the
clock framework yet.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
V2: - New patch
---
 drivers/watchdog/designware_wdt.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index a7b735979a..66621e8bb5 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -20,6 +20,7 @@
 
 struct designware_wdt_priv {
 	void __iomem	*base;
+	unsigned int	clk_khz;
 };
 
 /*
@@ -106,7 +107,7 @@ static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 	designware_wdt_stop(dev);
 
 	/* set timer in miliseconds */
-	designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
+	designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
 
 	designware_wdt_enable(priv->base);
 
@@ -122,6 +123,20 @@ static int designware_wdt_probe(struct udevice *dev)
 	if (!priv->base)
 		return -EINVAL;
 
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk clk;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return ret;
+
+	priv->clk_khz = clk_get_rate(&clk);
+	if (!priv->clk_khz)
+		return -EINVAL;
+#else
+	priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
+#endif
+
 	/* reset to disable the watchdog */
 	return designware_wdt_stop(dev);
 }
-- 
2.23.0

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-03 12:59 [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Marek Vasut
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 3/3] watchdog: designware: Optionally fetch clock from DT Marek Vasut
@ 2019-10-04  8:59 ` Ley Foon Tan
  2019-10-04 11:02   ` Marek Vasut
  2019-11-07 19:27 ` Simon Goldschmidt
  3 siblings, 1 reply; 16+ messages in thread
From: Ley Foon Tan @ 2019-10-04  8:59 UTC (permalink / raw)
  To: u-boot

On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut <marex@denx.de> wrote:
>
> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
> accordingly, no functional change. The S10 enables the WDT only in
> SPL, but does not enable it in U-Boot itself, hence disable it in
> the config again.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dalon Westergreen <dwesterg@gmail.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> V2: Use non-DM watchdog in SPL on S10
> ---
>  configs/socfpga_stratix10_defconfig       | 1 +
>  configs/socfpga_vining_fpga_defconfig     | 1 +

All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
socfpga_common.h is used by Gen5 and A10 platform.

Regards
Ley Foon


>  drivers/watchdog/Kconfig                  | 7 +++++++
>  include/configs/socfpga_common.h          | 3 ---
>  include/configs/socfpga_stratix10_socdk.h | 6 ++++--
>  scripts/config_whitelist.txt              | 1 -
>  6 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index ad83f50032..462082b67b 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig CONFIG_DESIGNWARE_WATCHDOG
> @@ -56,3 +56,4 @@ CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
>  CONFIG_USB_STORAGE=y
> +CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index 96f806ab5f..03c43fa8b9 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>  CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>  CONFIG_USB_GADGET_DWC2_OTG=y
>  CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index a66a9bcbe2..6fd9b0a177 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -36,6 +36,13 @@ config ULP_WATCHDOG
>         help
>           Say Y here to enable i.MX7ULP watchdog driver.
>
> +config DESIGNWARE_WATCHDOG
> +       bool "Designware watchdog timer support"
> +       select HW_WATCHDOG
> +       help
> +          Enable this to support Designware Watchdog Timer IP, present e.g.
> +          on Altera SoCFPGA SoCs.
> +
>  config WDT
>         bool "Enable driver model for watchdog timer drivers"
>         depends on DM
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index b11fe021a7..32b9131be0 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -104,12 +104,9 @@
>  /*
>   * L4 Watchdog
>   */
> -#ifdef CONFIG_HW_WATCHDOG
> -#define CONFIG_DESIGNWARE_WATCHDOG
>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
>  #define CONFIG_DW_WDT_CLOCK_KHZ                25000
>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
> -#endif
>
>  /*
>   * MMC Driver
> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
> index 7b55dd14da..353e08f982 100644
> --- a/include/configs/socfpga_stratix10_socdk.h
> +++ b/include/configs/socfpga_stratix10_socdk.h
> @@ -162,14 +162,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   */
>  #ifdef CONFIG_SPL_BUILD
>  #define CONFIG_HW_WATCHDOG
> -#define CONFIG_DESIGNWARE_WATCHDOG
> +#else
> +#undef CONFIG_HW_WATCHDOG
> +#undef CONFIG_DESIGNWARE_WATCHDOG
> +#endif
>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
>  #ifndef __ASSEMBLY__
>  unsigned int cm_get_l4_sys_free_clk_hz(void);
>  #define CONFIG_DW_WDT_CLOCK_KHZ                (cm_get_l4_sys_free_clk_hz() / 1000)
>  #endif
>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  3000
> -#endif
>
>  /*
>   * SPL memory layout
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index b18eab1707..839eda8c0f 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR
>  CONFIG_DEF_HWCONFIG
>  CONFIG_DELAY_ENVIRONMENT
>  CONFIG_DESIGNWARE_ETH
> -CONFIG_DESIGNWARE_WATCHDOG
>  CONFIG_DEVELOP
>  CONFIG_DEVICE_TREE_LIST
>  CONFIG_DFU_ALT
> --
> 2.23.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
@ 2019-10-04  9:26   ` Ley Foon Tan
  2019-11-07 17:45     ` Marek Vasut
  2019-11-07 19:30   ` Simon Goldschmidt
  2019-12-27  7:53   ` Jagan Teki
  2 siblings, 1 reply; 16+ messages in thread
From: Ley Foon Tan @ 2019-10-04  9:26 UTC (permalink / raw)
  To: u-boot

On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut <marex@denx.de> wrote:
>
> Convert the designware watchdog timer driver to DM and add DT probing
> support. Perform minor coding style clean up, like drop superfluous
> braces. There ought to be no functional change.

All watchdog DT nodes with compatible "snps,dw-wdt" need to add
"u-boot,dm-pre-reloc;".

>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dalon Westergreen <dwesterg@gmail.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> V2: - Support both DM and non-DM probing
>     - Fix watchdog stop handling by setting CR bit
> ---
>  configs/socfpga_stratix10_defconfig       |   2 +
>  configs/socfpga_vining_fpga_defconfig     |   1 +

Same here. All socfpga defconfig files need to add CONFIG_WDT.

>  drivers/watchdog/Kconfig                  |   2 +-
>  drivers/watchdog/designware_wdt.c         | 122 ++++++++++++++++++----
>  include/configs/socfpga_stratix10_socdk.h |   1 +
>  5 files changed, 104 insertions(+), 24 deletions(-)
>
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index 462082b67b..752fa545bd 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -57,3 +57,5 @@ CONFIG_DM_USB=y
>  CONFIG_USB_DWC2=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_DESIGNWARE_WATCHDOG=y
> +CONFIG_WDT=y
> +# CONFIG_SPL_WDT is not set
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index 03c43fa8b9..def7a3eca7 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>  CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>  CONFIG_USB_GADGET_DWC2_OTG=y
>  CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_WDT=y
>  CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 6fd9b0a177..bfb91af947 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -38,7 +38,7 @@ config ULP_WATCHDOG
>
>  config DESIGNWARE_WATCHDOG
>         bool "Designware watchdog timer support"
> -       select HW_WATCHDOG
> +       select HW_WATCHDOG if !WDT
>         help
>            Enable this to support Designware Watchdog Timer IP, present e.g.
>            on Altera SoCFPGA SoCs.
> diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
> index c668567c66..a7b735979a 100644
> --- a/drivers/watchdog/designware_wdt.c
> +++ b/drivers/watchdog/designware_wdt.c
> @@ -4,7 +4,8 @@
>   */
>
>  #include <common.h>
> -#include <watchdog.h>
> +#include <dm.h>
> +#include <wdt.h>
>  #include <asm/io.h>
>  #include <asm/utils.h>
>
> @@ -17,46 +18,51 @@
>  #define DW_WDT_CR_RMOD_VAL     0x00
>  #define DW_WDT_CRR_RESTART_VAL 0x76
>
> +struct designware_wdt_priv {
> +       void __iomem    *base;
> +};
> +
>  /*
>   * Set the watchdog time interval.
>   * Counter is 32 bit.
>   */
> -static int designware_wdt_settimeout(unsigned int timeout)
> +static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
> +                                    unsigned int timeout)
>  {
>         signed int i;
>
>         /* calculate the timeout range value */
> -       i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
> -       if (i > 15)
> -               i = 15;
> -       if (i < 0)
> -               i = 0;
> +       i = log_2_n_round_up(timeout * clk_khz) - 16;
> +       i = clamp(i, 0, 15);
> +
> +       writel(i | (i << 4), base + DW_WDT_TORR);
>
> -       writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
>         return 0;
>  }
>
> -static void designware_wdt_enable(void)
> +static void designware_wdt_enable(void __iomem *base)
>  {
> -       writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
> -             (0x1 << DW_WDT_CR_EN_OFFSET)),
> -             (CONFIG_DW_WDT_BASE + DW_WDT_CR));
> +       writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
> +               BIT(DW_WDT_CR_EN_OFFSET),
> +               base + DW_WDT_CR);
>  }
>
> -static unsigned int designware_wdt_is_enabled(void)
> +static unsigned int designware_wdt_is_enabled(void __iomem *base)
>  {
> -       unsigned long val;
> -       val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
> -       return val & 0x1;
> +       return readl(base + DW_WDT_CR) & BIT(0);
>  }
>
> -#if defined(CONFIG_HW_WATCHDOG)
> -void hw_watchdog_reset(void)
> +static void designware_wdt_reset_common(void __iomem *base)
>  {
> -       if (designware_wdt_is_enabled())
> +       if (designware_wdt_is_enabled(base))
>                 /* restart the watchdog counter */
> -               writel(DW_WDT_CRR_RESTART_VAL,
> -                      (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
> +               writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
> +}
> +
> +#if !CONFIG_IS_ENABLED(WDT)
> +void hw_watchdog_reset(void)
> +{
> +       designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
>  }
>
>  void hw_watchdog_init(void)
> @@ -64,10 +70,80 @@ void hw_watchdog_init(void)
>         /* reset to disable the watchdog */
>         hw_watchdog_reset();
>         /* set timer in miliseconds */
> -       designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
> +       designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
> +                                 CONFIG_DW_WDT_CLOCK_KHZ,
> +                                 CONFIG_WATCHDOG_TIMEOUT_MSECS);
>         /* enable the watchdog */
> -       designware_wdt_enable();
> +       designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
>         /* reset the watchdog */
>         hw_watchdog_reset();

In my "arm: socfpga: Convert drivers from struct to defines" patch
series, I have moved spl_early_init() to the beginning of
spl_board_f().
So, DM framework is initialized in early stage, you should able to use
DM for watchdog in SPL too.
But, maybe need to add a wrapper function to probe watchdog device and
start watchdog. Something like this:

uclass_get_device(UCLASS_WDT, 0, &dev);
wdt_start(dev, CONFIG_WATCHDOG_TIMEOUT_MSECS, 0);

>  }
> +#else
> +static int designware_wdt_reset(struct udevice *dev)
> +{
> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +       designware_wdt_reset_common(priv->base);
> +
> +       return 0;
> +}
> +
> +static int designware_wdt_stop(struct udevice *dev)
> +{
> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +       designware_wdt_reset(dev);
> +       writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
> +               priv->base + DW_WDT_CR);

Still no fixing clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to
disable watchdog.

> +
> +       return 0;
> +}
> +
> +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +{
> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +       designware_wdt_stop(dev);
> +
> +       /* set timer in miliseconds */
> +       designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
> +
> +       designware_wdt_enable(priv->base);
> +
> +       /* reset the watchdog */
> +       return designware_wdt_reset(dev);
> +}
> +
> +static int designware_wdt_probe(struct udevice *dev)
> +{
> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
> +

Need de-assert watchdog reset using reset framework function, reset_get_bulk().



> +       priv->base = dev_remap_addr(dev);
> +       if (!priv->base)
> +               return -EINVAL;
> +
> +       /* reset to disable the watchdog */
> +       return designware_wdt_stop(dev);
> +}
> +
> +static const struct wdt_ops designware_wdt_ops = {
> +       .start = designware_wdt_start,
> +       .reset = designware_wdt_reset,
> +       .stop = designware_wdt_stop,
> +};
> +
> +static const struct udevice_id designware_wdt_ids[] = {
> +       { .compatible = "snps,dw-wdt"},
> +       {}
> +};
> +
> +U_BOOT_DRIVER(designware_wdt) = {
> +       .name = "designware_wdt",
> +       .id = UCLASS_WDT,
> +       .of_match = designware_wdt_ids,
> +       .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
> +       .probe = designware_wdt_probe,
> +       .ops = &designware_wdt_ops,
> +       .flags = DM_FLAG_PRE_RELOC,
> +};
>  #endif
> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
> index 353e08f982..0c0c27000a 100644
> --- a/include/configs/socfpga_stratix10_socdk.h
> +++ b/include/configs/socfpga_stratix10_socdk.h
> @@ -161,6 +161,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   * L4 Watchdog
>   */
>  #ifdef CONFIG_SPL_BUILD
> +#undef CONFIG_WATCHDOG
>  #define CONFIG_HW_WATCHDOG
>  #else
>  #undef CONFIG_HW_WATCHDOG
> --
> 2.23.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-04  8:59 ` [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Ley Foon Tan
@ 2019-10-04 11:02   ` Marek Vasut
  2019-10-10  6:28     ` Ley Foon Tan
  0 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2019-10-04 11:02 UTC (permalink / raw)
  To: u-boot

On 10/4/19 10:59 AM, Ley Foon Tan wrote:
> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>
>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
>> accordingly, no functional change. The S10 enables the WDT only in
>> SPL, but does not enable it in U-Boot itself, hence disable it in
>> the config again.
>> ---
>> V2: Use non-DM watchdog in SPL on S10
>> ---
>>  configs/socfpga_stratix10_defconfig       | 1 +
>>  configs/socfpga_vining_fpga_defconfig     | 1 +
> 
> All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
> socfpga_common.h is used by Gen5 and A10 platform.

Only those which defined CONFIG_HW_WATCHDOG need to enable the
CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)

[...]

>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
>> index b11fe021a7..32b9131be0 100644
>> --- a/include/configs/socfpga_common.h
>> +++ b/include/configs/socfpga_common.h
>> @@ -104,12 +104,9 @@
>>  /*
>>   * L4 Watchdog
>>   */
>> -#ifdef CONFIG_HW_WATCHDOG
>> -#define CONFIG_DESIGNWARE_WATCHDOG
>>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
>>  #define CONFIG_DW_WDT_CLOCK_KHZ                25000
>>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
>> -#endif

[...]

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-04 11:02   ` Marek Vasut
@ 2019-10-10  6:28     ` Ley Foon Tan
  2019-10-10  7:15       ` Marek Vasut
  0 siblings, 1 reply; 16+ messages in thread
From: Ley Foon Tan @ 2019-10-10  6:28 UTC (permalink / raw)
  To: u-boot

On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut <marex@denx.de> wrote:
>
> On 10/4/19 10:59 AM, Ley Foon Tan wrote:
> > On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
> >>
> >> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
> >> accordingly, no functional change. The S10 enables the WDT only in
> >> SPL, but does not enable it in U-Boot itself, hence disable it in
> >> the config again.
> >> ---
> >> V2: Use non-DM watchdog in SPL on S10
> >> ---
> >>  configs/socfpga_stratix10_defconfig       | 1 +
> >>  configs/socfpga_vining_fpga_defconfig     | 1 +
> >
> > All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
> > socfpga_common.h is used by Gen5 and A10 platform.
>
> Only those which defined CONFIG_HW_WATCHDOG need to enable the
> CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)

$ git grep socfpga_common.h
include/configs/socfpga_arria10_socdk.h:#include <configs/socfpga_common.h>
include/configs/socfpga_arria5_socdk.h:#include <configs/socfpga_common.h>
include/configs/socfpga_cyclone5_socdk.h:#include <configs/socfpga_common.h>
include/configs/socfpga_dbm_soc1.h:#include <configs/socfpga_common.h>
include/configs/socfpga_de0_nano_soc.h:#include <configs/socfpga_common.h>
include/configs/socfpga_de10_nano.h:#include <configs/socfpga_common.h>
include/configs/socfpga_de1_soc.h:#include <configs/socfpga_common.h>
include/configs/socfpga_is1.h:#include <configs/socfpga_common.h>
include/configs/socfpga_mcvevk.h:#include <configs/socfpga_common.h>
include/configs/socfpga_sockit.h:#include <configs/socfpga_common.h>
include/configs/socfpga_socrates.h:#include <configs/socfpga_common.h>
include/configs/socfpga_sr1500.h:#include <configs/socfpga_common.h>
include/configs/socfpga_vining_fpga.h:#include <configs/socfpga_common.h>

These platforms include socfpga_common.h file, so their _defconfig
need to update too.

>
> [...]
>
> >> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> >> index b11fe021a7..32b9131be0 100644
> >> --- a/include/configs/socfpga_common.h
> >> +++ b/include/configs/socfpga_common.h
> >> @@ -104,12 +104,9 @@
> >>  /*
> >>   * L4 Watchdog
> >>   */
> >> -#ifdef CONFIG_HW_WATCHDOG
> >> -#define CONFIG_DESIGNWARE_WATCHDOG
> >>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
> >>  #define CONFIG_DW_WDT_CLOCK_KHZ                25000
> >>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
> >> -#endif
>
> [...]

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-10  6:28     ` Ley Foon Tan
@ 2019-10-10  7:15       ` Marek Vasut
  2019-10-11  9:51         ` Ley Foon Tan
  0 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2019-10-10  7:15 UTC (permalink / raw)
  To: u-boot

On 10/10/19 8:28 AM, Ley Foon Tan wrote:
> On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut wrote:
>>
>> On 10/4/19 10:59 AM, Ley Foon Tan wrote:
>>> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>>>
>>>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
>>>> accordingly, no functional change. The S10 enables the WDT only in
>>>> SPL, but does not enable it in U-Boot itself, hence disable it in
>>>> the config again.
>>>> ---
>>>> V2: Use non-DM watchdog in SPL on S10
>>>> ---
>>>>  configs/socfpga_stratix10_defconfig       | 1 +
>>>>  configs/socfpga_vining_fpga_defconfig     | 1 +
>>>
>>> All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
>>> socfpga_common.h is used by Gen5 and A10 platform.
>>
>> Only those which defined CONFIG_HW_WATCHDOG need to enable the
>> CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)
> 
> $ git grep socfpga_common.h
> include/configs/socfpga_arria10_socdk.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_arria5_socdk.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_cyclone5_socdk.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_dbm_soc1.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_de0_nano_soc.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_de10_nano.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_de1_soc.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_is1.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_mcvevk.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_sockit.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_socrates.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_sr1500.h:#include <configs/socfpga_common.h>
> include/configs/socfpga_vining_fpga.h:#include <configs/socfpga_common.h>
> 
> These platforms include socfpga_common.h file, so their _defconfig
> need to update too.

They don't enable HW_WATCHDOG, so it doesn't ... or ?

>> [...]
>>
>>>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
>>>> index b11fe021a7..32b9131be0 100644
>>>> --- a/include/configs/socfpga_common.h
>>>> +++ b/include/configs/socfpga_common.h
>>>> @@ -104,12 +104,9 @@
>>>>  /*
>>>>   * L4 Watchdog
>>>>   */
>>>> -#ifdef CONFIG_HW_WATCHDOG
>>>> -#define CONFIG_DESIGNWARE_WATCHDOG
>>>>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
>>>>  #define CONFIG_DW_WDT_CLOCK_KHZ                25000
>>>>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
>>>> -#endif
>>
>> [...]


-- 
Best regards,
Marek Vasut

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-10  7:15       ` Marek Vasut
@ 2019-10-11  9:51         ` Ley Foon Tan
  2019-11-07 17:46           ` Marek Vasut
  0 siblings, 1 reply; 16+ messages in thread
From: Ley Foon Tan @ 2019-10-11  9:51 UTC (permalink / raw)
  To: u-boot

On Thu, Oct 10, 2019 at 3:47 PM Marek Vasut <marex@denx.de> wrote:
>
> On 10/10/19 8:28 AM, Ley Foon Tan wrote:
> > On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut wrote:
> >>
> >> On 10/4/19 10:59 AM, Ley Foon Tan wrote:
> >>> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
> >>>>
> >>>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
> >>>> accordingly, no functional change. The S10 enables the WDT only in
> >>>> SPL, but does not enable it in U-Boot itself, hence disable it in
> >>>> the config again.
> >>>> ---
> >>>> V2: Use non-DM watchdog in SPL on S10
> >>>> ---
> >>>>  configs/socfpga_stratix10_defconfig       | 1 +
> >>>>  configs/socfpga_vining_fpga_defconfig     | 1 +
> >>>
> >>> All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
> >>> socfpga_common.h is used by Gen5 and A10 platform.
> >>
> >> Only those which defined CONFIG_HW_WATCHDOG need to enable the
> >> CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)
> >
> > $ git grep socfpga_common.h
> > include/configs/socfpga_arria10_socdk.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_arria5_socdk.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_cyclone5_socdk.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_dbm_soc1.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_de0_nano_soc.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_de10_nano.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_de1_soc.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_is1.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_mcvevk.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_sockit.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_socrates.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_sr1500.h:#include <configs/socfpga_common.h>
> > include/configs/socfpga_vining_fpga.h:#include <configs/socfpga_common.h>
> >
> > These platforms include socfpga_common.h file, so their _defconfig
> > need to update too.
>
> They don't enable HW_WATCHDOG, so it doesn't ... or ?
Sorry, I see wrongly. I thought HW_WATCHDOG is defined in socfpga_common.h.
Then no problem now.

Regards
Ley Foon
>
> >> [...]
> >>
> >>>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> >>>> index b11fe021a7..32b9131be0 100644
> >>>> --- a/include/configs/socfpga_common.h
> >>>> +++ b/include/configs/socfpga_common.h
> >>>> @@ -104,12 +104,9 @@
> >>>>  /*
> >>>>   * L4 Watchdog
> >>>>   */
> >>>> -#ifdef CONFIG_HW_WATCHDOG
> >>>> -#define CONFIG_DESIGNWARE_WATCHDOG
> >>>>  #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
> >>>>  #define CONFIG_DW_WDT_CLOCK_KHZ                25000
> >>>>  #define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
> >>>> -#endif
> >>
> >> [...]
>
>
> --
> Best regards,
> Marek Vasut

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-10-04  9:26   ` Ley Foon Tan
@ 2019-11-07 17:45     ` Marek Vasut
  0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2019-11-07 17:45 UTC (permalink / raw)
  To: u-boot

On 10/4/19 11:26 AM, Ley Foon Tan wrote:
> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>
>> Convert the designware watchdog timer driver to DM and add DT probing
>> support. Perform minor coding style clean up, like drop superfluous
>> braces. There ought to be no functional change.
> 
> All watchdog DT nodes with compatible "snps,dw-wdt" need to add
> "u-boot,dm-pre-reloc;".

Only those boards which actually use the WDT, right ? That is, these two
boards below.

>> ---
>> V2: - Support both DM and non-DM probing
>>     - Fix watchdog stop handling by setting CR bit
>> ---
>>  configs/socfpga_stratix10_defconfig       |   2 +
>>  configs/socfpga_vining_fpga_defconfig     |   1 +
> 
> Same here. All socfpga defconfig files need to add CONFIG_WDT.

Only those two, since only those two boards enable the WDT, no ?

[...]

>>  void hw_watchdog_init(void)
>> @@ -64,10 +70,80 @@ void hw_watchdog_init(void)
>>         /* reset to disable the watchdog */
>>         hw_watchdog_reset();
>>         /* set timer in miliseconds */
>> -       designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
>> +       designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
>> +                                 CONFIG_DW_WDT_CLOCK_KHZ,
>> +                                 CONFIG_WATCHDOG_TIMEOUT_MSECS);
>>         /* enable the watchdog */
>> -       designware_wdt_enable();
>> +       designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
>>         /* reset the watchdog */
>>         hw_watchdog_reset();
> 
> In my "arm: socfpga: Convert drivers from struct to defines" patch
> series, I have moved spl_early_init() to the beginning of
> spl_board_f().
> So, DM framework is initialized in early stage, you should able to use
> DM for watchdog in SPL too.
> But, maybe need to add a wrapper function to probe watchdog device and
> start watchdog. Something like this:
> 
> uclass_get_device(UCLASS_WDT, 0, &dev);
> wdt_start(dev, CONFIG_WATCHDOG_TIMEOUT_MSECS, 0);

Except this driver is not used only on SoCFPGA.
So the question is, with your conversion series, will there be boards
left which use non-DM version of this WDT driver ?

>>  }
>> +#else
>> +static int designware_wdt_reset(struct udevice *dev)
>> +{
>> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +       designware_wdt_reset_common(priv->base);
>> +
>> +       return 0;
>> +}
>> +
>> +static int designware_wdt_stop(struct udevice *dev)
>> +{
>> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +       designware_wdt_reset(dev);
>> +       writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
>> +               priv->base + DW_WDT_CR);
> 
> Still no fixing clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to
> disable watchdog.

I guess we an just write 0 to the CR register and get rid of RMOD_VAL
altogether ?

>> +
>> +       return 0;
>> +}
>> +
>> +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
>> +{
>> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +       designware_wdt_stop(dev);
>> +
>> +       /* set timer in miliseconds */
>> +       designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
>> +
>> +       designware_wdt_enable(priv->base);
>> +
>> +       /* reset the watchdog */
>> +       return designware_wdt_reset(dev);
>> +}
>> +
>> +static int designware_wdt_probe(struct udevice *dev)
>> +{
>> +       struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
> 
> Need de-assert watchdog reset using reset framework function, reset_get_bulk().

Ah yes, and make it presumably optional.

[...]

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-11  9:51         ` Ley Foon Tan
@ 2019-11-07 17:46           ` Marek Vasut
  0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2019-11-07 17:46 UTC (permalink / raw)
  To: u-boot

On 10/11/19 11:51 AM, Ley Foon Tan wrote:
> On Thu, Oct 10, 2019 at 3:47 PM Marek Vasut wrote:
>>
>> On 10/10/19 8:28 AM, Ley Foon Tan wrote:
>>> On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut wrote:
>>>>
>>>> On 10/4/19 10:59 AM, Ley Foon Tan wrote:
>>>>> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>>>>>
>>>>>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
>>>>>> accordingly, no functional change. The S10 enables the WDT only in
>>>>>> SPL, but does not enable it in U-Boot itself, hence disable it in
>>>>>> the config again.
>>>>>> ---
>>>>>> V2: Use non-DM watchdog in SPL on S10
>>>>>> ---
>>>>>>  configs/socfpga_stratix10_defconfig       | 1 +
>>>>>>  configs/socfpga_vining_fpga_defconfig     | 1 +
>>>>>
>>>>> All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
>>>>> socfpga_common.h is used by Gen5 and A10 platform.
>>>>
>>>> Only those which defined CONFIG_HW_WATCHDOG need to enable the
>>>> CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)
>>>
>>> $ git grep socfpga_common.h
>>> include/configs/socfpga_arria10_socdk.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_arria5_socdk.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_cyclone5_socdk.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_dbm_soc1.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_de0_nano_soc.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_de10_nano.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_de1_soc.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_is1.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_mcvevk.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_sockit.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_socrates.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_sr1500.h:#include <configs/socfpga_common.h>
>>> include/configs/socfpga_vining_fpga.h:#include <configs/socfpga_common.h>
>>>
>>> These platforms include socfpga_common.h file, so their _defconfig
>>> need to update too.
>>
>> They don't enable HW_WATCHDOG, so it doesn't ... or ?
> Sorry, I see wrongly. I thought HW_WATCHDOG is defined in socfpga_common.h.
> Then no problem now.

Sorry for the late reply.

Are we OK with this patch then ?

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
  2019-10-03 12:59 [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Marek Vasut
                   ` (2 preceding siblings ...)
  2019-10-04  8:59 ` [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Ley Foon Tan
@ 2019-11-07 19:27 ` Simon Goldschmidt
  3 siblings, 0 replies; 16+ messages in thread
From: Simon Goldschmidt @ 2019-11-07 19:27 UTC (permalink / raw)
  To: u-boot

Am 03.10.2019 um 14:59 schrieb Marek Vasut:
> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
> accordingly, no functional change. The S10 enables the WDT only in
> SPL, but does not enable it in U-Boot itself, hence disable it in
> the config again.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dalon Westergreen <dwesterg@gmail.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

> ---
> V2: Use non-DM watchdog in SPL on S10
> ---
>   configs/socfpga_stratix10_defconfig       | 1 +
>   configs/socfpga_vining_fpga_defconfig     | 1 +
>   drivers/watchdog/Kconfig                  | 7 +++++++
>   include/configs/socfpga_common.h          | 3 ---
>   include/configs/socfpga_stratix10_socdk.h | 6 ++++--
>   scripts/config_whitelist.txt              | 1 -
>   6 files changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index ad83f50032..462082b67b 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -56,3 +56,4 @@ CONFIG_USB=y
>   CONFIG_DM_USB=y
>   CONFIG_USB_DWC2=y
>   CONFIG_USB_STORAGE=y
> +CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index 96f806ab5f..03c43fa8b9 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>   CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>   CONFIG_USB_GADGET_DWC2_OTG=y
>   CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index a66a9bcbe2..6fd9b0a177 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -36,6 +36,13 @@ config ULP_WATCHDOG
>   	help
>   	  Say Y here to enable i.MX7ULP watchdog driver.
>   
> +config DESIGNWARE_WATCHDOG
> +	bool "Designware watchdog timer support"
> +	select HW_WATCHDOG
> +	help
> +	   Enable this to support Designware Watchdog Timer IP, present e.g.
> +	   on Altera SoCFPGA SoCs.
> +
>   config WDT
>   	bool "Enable driver model for watchdog timer drivers"
>   	depends on DM
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index b11fe021a7..32b9131be0 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -104,12 +104,9 @@
>   /*
>    * L4 Watchdog
>    */
> -#ifdef CONFIG_HW_WATCHDOG
> -#define CONFIG_DESIGNWARE_WATCHDOG
>   #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
>   #define CONFIG_DW_WDT_CLOCK_KHZ		25000
>   #define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
> -#endif
>   
>   /*
>    * MMC Driver
> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
> index 7b55dd14da..353e08f982 100644
> --- a/include/configs/socfpga_stratix10_socdk.h
> +++ b/include/configs/socfpga_stratix10_socdk.h
> @@ -162,14 +162,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>    */
>   #ifdef CONFIG_SPL_BUILD
>   #define CONFIG_HW_WATCHDOG
> -#define CONFIG_DESIGNWARE_WATCHDOG
> +#else
> +#undef CONFIG_HW_WATCHDOG
> +#undef CONFIG_DESIGNWARE_WATCHDOG
> +#endif
>   #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
>   #ifndef __ASSEMBLY__
>   unsigned int cm_get_l4_sys_free_clk_hz(void);
>   #define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
>   #endif
>   #define CONFIG_WATCHDOG_TIMEOUT_MSECS	3000
> -#endif
>   
>   /*
>    * SPL memory layout
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index b18eab1707..839eda8c0f 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR
>   CONFIG_DEF_HWCONFIG
>   CONFIG_DELAY_ENVIRONMENT
>   CONFIG_DESIGNWARE_ETH
> -CONFIG_DESIGNWARE_WATCHDOG
>   CONFIG_DEVELOP
>   CONFIG_DEVICE_TREE_LIST
>   CONFIG_DFU_ALT
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
  2019-10-04  9:26   ` Ley Foon Tan
@ 2019-11-07 19:30   ` Simon Goldschmidt
  2019-11-07 19:37     ` Marek Vasut
  2019-12-27  7:53   ` Jagan Teki
  2 siblings, 1 reply; 16+ messages in thread
From: Simon Goldschmidt @ 2019-11-07 19:30 UTC (permalink / raw)
  To: u-boot

Am 03.10.2019 um 14:59 schrieb Marek Vasut:
> Convert the designware watchdog timer driver to DM and add DT probing
> support. Perform minor coding style clean up, like drop superfluous
> braces. There ought to be no functional change.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dalon Westergreen <dwesterg@gmail.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> V2: - Support both DM and non-DM probing
>      - Fix watchdog stop handling by setting CR bit
> ---
>   configs/socfpga_stratix10_defconfig       |   2 +
>   configs/socfpga_vining_fpga_defconfig     |   1 +
>   drivers/watchdog/Kconfig                  |   2 +-
>   drivers/watchdog/designware_wdt.c         | 122 ++++++++++++++++++----
>   include/configs/socfpga_stratix10_socdk.h |   1 +
>   5 files changed, 104 insertions(+), 24 deletions(-)
> 
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index 462082b67b..752fa545bd 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -57,3 +57,5 @@ CONFIG_DM_USB=y
>   CONFIG_USB_DWC2=y
>   CONFIG_USB_STORAGE=y
>   CONFIG_DESIGNWARE_WATCHDOG=y
> +CONFIG_WDT=y
> +# CONFIG_SPL_WDT is not set
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index 03c43fa8b9..def7a3eca7 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>   CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>   CONFIG_USB_GADGET_DWC2_OTG=y
>   CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_WDT=y
>   CONFIG_DESIGNWARE_WATCHDOG=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 6fd9b0a177..bfb91af947 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -38,7 +38,7 @@ config ULP_WATCHDOG
>   
>   config DESIGNWARE_WATCHDOG
>   	bool "Designware watchdog timer support"
> -	select HW_WATCHDOG
> +	select HW_WATCHDOG if !WDT
>   	help
>   	   Enable this to support Designware Watchdog Timer IP, present e.g.
>   	   on Altera SoCFPGA SoCs.
> diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
> index c668567c66..a7b735979a 100644
> --- a/drivers/watchdog/designware_wdt.c
> +++ b/drivers/watchdog/designware_wdt.c
> @@ -4,7 +4,8 @@
>    */
>   
>   #include <common.h>
> -#include <watchdog.h>
> +#include <dm.h>
> +#include <wdt.h>
>   #include <asm/io.h>
>   #include <asm/utils.h>
>   
> @@ -17,46 +18,51 @@
>   #define DW_WDT_CR_RMOD_VAL	0x00
>   #define DW_WDT_CRR_RESTART_VAL	0x76
>   
> +struct designware_wdt_priv {
> +	void __iomem	*base;
> +};
> +
>   /*
>    * Set the watchdog time interval.
>    * Counter is 32 bit.
>    */
> -static int designware_wdt_settimeout(unsigned int timeout)
> +static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
> +				     unsigned int timeout)
>   {
>   	signed int i;
>   
>   	/* calculate the timeout range value */
> -	i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
> -	if (i > 15)
> -		i = 15;
> -	if (i < 0)
> -		i = 0;
> +	i = log_2_n_round_up(timeout * clk_khz) - 16;
> +	i = clamp(i, 0, 15);
> +
> +	writel(i | (i << 4), base + DW_WDT_TORR);
>   
> -	writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
>   	return 0;
>   }
>   
> -static void designware_wdt_enable(void)
> +static void designware_wdt_enable(void __iomem *base)
>   {
> -	writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
> -	      (0x1 << DW_WDT_CR_EN_OFFSET)),
> -	      (CONFIG_DW_WDT_BASE + DW_WDT_CR));
> +	writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
> +		BIT(DW_WDT_CR_EN_OFFSET),
> +		base + DW_WDT_CR);
>   }
>   
> -static unsigned int designware_wdt_is_enabled(void)
> +static unsigned int designware_wdt_is_enabled(void __iomem *base)
>   {
> -	unsigned long val;
> -	val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
> -	return val & 0x1;
> +	return readl(base + DW_WDT_CR) & BIT(0);
>   }
>   
> -#if defined(CONFIG_HW_WATCHDOG)
> -void hw_watchdog_reset(void)
> +static void designware_wdt_reset_common(void __iomem *base)
>   {
> -	if (designware_wdt_is_enabled())
> +	if (designware_wdt_is_enabled(base))
>   		/* restart the watchdog counter */
> -		writel(DW_WDT_CRR_RESTART_VAL,
> -		       (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
> +		writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
> +}
> +
> +#if !CONFIG_IS_ENABLED(WDT)
> +void hw_watchdog_reset(void)
> +{
> +	designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
>   }
>   
>   void hw_watchdog_init(void)
> @@ -64,10 +70,80 @@ void hw_watchdog_init(void)
>   	/* reset to disable the watchdog */
>   	hw_watchdog_reset();
>   	/* set timer in miliseconds */
> -	designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
> +	designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
> +				  CONFIG_DW_WDT_CLOCK_KHZ,
> +				  CONFIG_WATCHDOG_TIMEOUT_MSECS);
>   	/* enable the watchdog */
> -	designware_wdt_enable();
> +	designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
>   	/* reset the watchdog */
>   	hw_watchdog_reset();
>   }
> +#else
> +static int designware_wdt_reset(struct udevice *dev)
> +{
> +	struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +	designware_wdt_reset_common(priv->base);
> +
> +	return 0;
> +}
> +
> +static int designware_wdt_stop(struct udevice *dev)
> +{
> +	struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +	designware_wdt_reset(dev);
> +	writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
> +		priv->base + DW_WDT_CR);
> +
> +	return 0;
> +}
> +
> +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +{
> +	struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +	designware_wdt_stop(dev);
> +
> +	/* set timer in miliseconds */
> +	designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
> +
> +	designware_wdt_enable(priv->base);
> +
> +	/* reset the watchdog */
> +	return designware_wdt_reset(dev);
> +}
> +
> +static int designware_wdt_probe(struct udevice *dev)
> +{
> +	struct designware_wdt_priv *priv = dev_get_priv(dev);
> +
> +	priv->base = dev_remap_addr(dev);
> +	if (!priv->base)
> +		return -EINVAL;
> +
> +	/* reset to disable the watchdog */
> +	return designware_wdt_stop(dev);
> +}
> +
> +static const struct wdt_ops designware_wdt_ops = {
> +	.start = designware_wdt_start,
> +	.reset = designware_wdt_reset,
> +	.stop = designware_wdt_stop,
> +};
> +
> +static const struct udevice_id designware_wdt_ids[] = {
> +	{ .compatible = "snps,dw-wdt"},
> +	{}
> +};
> +
> +U_BOOT_DRIVER(designware_wdt) = {
> +	.name = "designware_wdt",
> +	.id = UCLASS_WDT,
> +	.of_match = designware_wdt_ids,
> +	.priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
> +	.probe = designware_wdt_probe,
> +	.ops = &designware_wdt_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
>   #endif
> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
> index 353e08f982..0c0c27000a 100644
> --- a/include/configs/socfpga_stratix10_socdk.h
> +++ b/include/configs/socfpga_stratix10_socdk.h
> @@ -161,6 +161,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>    * L4 Watchdog
>    */
>   #ifdef CONFIG_SPL_BUILD
> +#undef CONFIG_WATCHDOG

I somehow missed this series.
Why is this line here?

Other than that:
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Regards,
Simon

>   #define CONFIG_HW_WATCHDOG
>   #else
>   #undef CONFIG_HW_WATCHDOG
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-11-07 19:30   ` Simon Goldschmidt
@ 2019-11-07 19:37     ` Marek Vasut
  0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2019-11-07 19:37 UTC (permalink / raw)
  To: u-boot

On 11/7/19 8:30 PM, Simon Goldschmidt wrote:
[...]

>> diff --git a/include/configs/socfpga_stratix10_socdk.h
>> b/include/configs/socfpga_stratix10_socdk.h
>> index 353e08f982..0c0c27000a 100644
>> --- a/include/configs/socfpga_stratix10_socdk.h
>> +++ b/include/configs/socfpga_stratix10_socdk.h
>> @@ -161,6 +161,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>    * L4 Watchdog
>>    */
>>   #ifdef CONFIG_SPL_BUILD
>> +#undef CONFIG_WATCHDOG
> 
> I somehow missed this series.
> Why is this line here?

To avoid using DM watchdog in SPL on S10.

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
  2019-10-04  9:26   ` Ley Foon Tan
  2019-11-07 19:30   ` Simon Goldschmidt
@ 2019-12-27  7:53   ` Jagan Teki
  2020-01-06 14:15     ` Marek Vasut
  2 siblings, 1 reply; 16+ messages in thread
From: Jagan Teki @ 2019-12-27  7:53 UTC (permalink / raw)
  To: u-boot

Hi Marek,

On Thu, Oct 3, 2019 at 6:30 PM Marek Vasut <marex@denx.de> wrote:
>
> Convert the designware watchdog timer driver to DM and add DT probing
> support. Perform minor coding style clean up, like drop superfluous
> braces. There ought to be no functional change.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dalon Westergreen <dwesterg@gmail.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> V2: - Support both DM and non-DM probing
>     - Fix watchdog stop handling by setting CR bit
> ---

Please resend on top of master, would like to check it on rockchip.

Jagan.

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing
  2019-12-27  7:53   ` Jagan Teki
@ 2020-01-06 14:15     ` Marek Vasut
  0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2020-01-06 14:15 UTC (permalink / raw)
  To: u-boot

On 12/27/19 8:53 AM, Jagan Teki wrote:
> Hi Marek,
> 
> On Thu, Oct 3, 2019 at 6:30 PM Marek Vasut <marex@denx.de> wrote:
>>
>> Convert the designware watchdog timer driver to DM and add DT probing
>> support. Perform minor coding style clean up, like drop superfluous
>> braces. There ought to be no functional change.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Chin Liang See <chin.liang.see@intel.com>
>> Cc: Dalon Westergreen <dwesterg@gmail.com>
>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>> Cc: Jagan Teki <jagan@amarulasolutions.com>
>> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
>> Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
>> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
>> ---
>> V2: - Support both DM and non-DM probing
>>     - Fix watchdog stop handling by setting CR bit
>> ---
> 
> Please resend on top of master, would like to check it on rockchip.

Done, please give it a try.

^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-01-06 14:15 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-03 12:59 [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Marek Vasut
2019-10-03 12:59 ` [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing Marek Vasut
2019-10-04  9:26   ` Ley Foon Tan
2019-11-07 17:45     ` Marek Vasut
2019-11-07 19:30   ` Simon Goldschmidt
2019-11-07 19:37     ` Marek Vasut
2019-12-27  7:53   ` Jagan Teki
2020-01-06 14:15     ` Marek Vasut
2019-10-03 12:59 ` [U-Boot] [PATCH V2 3/3] watchdog: designware: Optionally fetch clock from DT Marek Vasut
2019-10-04  8:59 ` [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig Ley Foon Tan
2019-10-04 11:02   ` Marek Vasut
2019-10-10  6:28     ` Ley Foon Tan
2019-10-10  7:15       ` Marek Vasut
2019-10-11  9:51         ` Ley Foon Tan
2019-11-07 17:46           ` Marek Vasut
2019-11-07 19:27 ` Simon Goldschmidt

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