From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f182.google.com (mail-qk1-f182.google.com [209.85.222.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61F0B622 for ; Fri, 9 Sep 2022 07:10:52 +0000 (UTC) Received: by mail-qk1-f182.google.com with SMTP id 3so163156qka.5 for ; Fri, 09 Sep 2022 00:10:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date; bh=GbISm7ahSLrwT2Au2tPllsLxCWm8oBE76/YUTIUdxx0=; b=QgOZ94yQKc2ixl11yGnGeZTARgUUbjqqe67AmOp7GUPn+04a2NfkPBWPC8gLcs/GrZ bmHC1aDFgZhVcER0u59Z8IfcIB/Wb4lznkEOgCxJhTiE+a4XeuESZo0sZMIa3lcyOJ96 tVmG/otnYzuNCasxx/fRVVYydO771JPHpb1qI4rtMw8vtnlQ/YlBzTEwPHgdxnWJ0pEk PuSvH/Nerw4/DqPgQb53UA9RRMDxYrcKOwuDaSergWHNMbmXgaFY1vSGQBti9MvRC58Q d7Yl/93bbcV66erbph5BKD9gMDIzEeqMZ6fivdKZiwQdNW8iDc3iwsAi1V3InkMLsY+d aDeg== X-Gm-Message-State: ACgBeo07ot/op9atYhyt7nwiQ9HtH5Sst9x4Bzwg0eoDPA9HFeLQaJ8v I3RIXu3pvSmnJz0lsFTxCyxFiNf7QnZ1pw== X-Google-Smtp-Source: AA6agR7Ozk1Jw5opFlq+AGefjnLqqz2KyB29kuqDC6JaZrwc5xibJa7h+7qEUR0kShPyDBQoZL1FmA== X-Received: by 2002:a05:620a:448b:b0:6bb:d0c1:b113 with SMTP id x11-20020a05620a448b00b006bbd0c1b113mr9246554qkp.719.1662707450946; Fri, 09 Sep 2022 00:10:50 -0700 (PDT) Received: from mail-yb1-f177.google.com (mail-yb1-f177.google.com. [209.85.219.177]) by smtp.gmail.com with ESMTPSA id o25-20020a05620a0d5900b006bc1512986esm767639qkl.97.2022.09.09.00.10.49 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 00:10:50 -0700 (PDT) Received: by mail-yb1-f177.google.com with SMTP id b136so1395662yba.2 for ; Fri, 09 Sep 2022 00:10:49 -0700 (PDT) X-Received: by 2002:a25:3851:0:b0:6ad:9cba:9708 with SMTP id f78-20020a253851000000b006ad9cba9708mr8823957yba.36.1662707449504; Fri, 09 Sep 2022 00:10:49 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20220815050815.22340-1-samuel@sholland.org> <20220815050815.22340-7-samuel@sholland.org> <20220815141159.10edeba5@donnerap.cambridge.arm.com> <3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com> <932aaefd-e2ca-ef26-bf30-e315fb271ec5@sholland.org> <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> <44b6f601-1a11-aacf-5592-5b61550afb9f@microchip.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 09:10:37 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree To: Samuel Holland Cc: Conor Dooley , Andre Przywara , Jessica Clarke , devicetree , Albert Ou , Linux Kernel Mailing List , Jernej Skrabec , "Lad, Prabhakar" , Chen-Yu Tsai , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv , linux-sunxi@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Samuel, On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland wrote: > On 8/22/22 10:29 AM, Jessica Clarke wrote: > > On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote: > >> On 22/08/2022 13:31, Geert Uytterhoeven wrote: > >>>> Do you think this is worth doing? Or are you just providing an > >>>> example of what could be done? > >>> > >>> Just some brainstorming... > >>> > >>>> Where would you envisage putting these macros? I forget the order > >>>> of the CPP operations that are done, can they be put in the dts? > >>> > >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the > >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > >> > >> Right, one level up but ~the same result. > >> > >>>>> Nice! But it's gonna be a very large interrupt-map. > >>>> > >>>> I quite like the idea of not duplicating files across the archs > >>>> if it can be helped, but not at the expense of making them hard to > >>>> understand & I feel like unfortunately the large interrupt map is > >>>> in that territory. > >>> > >>> I feel the same. > >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) > >>> is a risk for making mistakes. > >>> > >>> So personally, I'm in favor of teaching dtc arithmetic, so we can > >>> handle the offset in SOC_PERIPHERAL_IRQ(). > >> > >> Yup, in the same boat here. mayb I'll get bored enough to bite.. > > > > Note that GPL=E2=80=99ed dtc isn=E2=80=99t the only implementation. Fre= eBSD uses a > > BSD-licensed implementation[1] and so adding new features like this to > > GPL dtc that actually get used would require us to reimplement it too. > > I don=E2=80=99t know how much effort it would be but please keep this i= n mind. > > I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2.= I like > that it only affects the DT source, and does not leak into the DTB. We st= ill > have the freedom to switch to using arithmetic later when all of the tool= s > support it. May I suggest an alternative solution, which would be more generic, and can be extended to other/more CPU cores easily: Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM() resp. RISCV() macros: ARM(interrupts =3D ;) RISCV(interrupts =3D <412 IRQ_TYPE_LEVEL_HIGH>;) The same construct can be used for e.g. interrupt-parent. The ARM .dts would define: #define ARM(x...) x #define RISCV(x....) before including the .dtsi. The RISC-V DTS would define instead: #define ARM(x...) #define RISCV(x...) x Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in arch/arm/include/asm/unified.h. Note that this is not exactly a new issue. It's fairly common for SoCs to have separate application and real-time cores, and on-SoC devices may be wired to multiple interrupt controllers serving the AP resp. RT cores. If both core sets are ARM, both interrupt controllers may be GIC, and the problem may be less severe and just need a different #interrupt-parent. But in case of ARM vs. RISC-V, or different wirings from devices to interrupt controllers, you do need completely different interrupts properties. > My other concern is that the big interrupt-map property would make DT ove= rlays > even more painful to deal with. I don't think overlays can append to a pr= operty, > only replace it. Indeed, overlays can only add/replace/delete properties. Same for plain DTS files, BTW. But I agree having /append-property/ would be useful in general. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE9B8ECAAD3 for ; Fri, 9 Sep 2022 07:18:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6bA0+2vQZ1LypF/eOAPdHwPHe+tKMk6/VunwTmtJFBE=; b=hGcrLOgmi2I7RG vDka8e236o+QrczEZl5bNuzu+vaK61CH78d84UkfwnIwd61VGWbm7ZIuk+ontalQqfJ9lsI32Dr28 ZXf7kDSI5o5t8/73dx08tvzRvmefeiPsll/vok1vwJzlk5UApPfR74dgzTMRV17sxI3MHoLiLV/XA fUuX4Pny1NLYFATotmom+uY8AL1/a5CPxeeWWGHSQdSeMTaxzfYpctYrRRJsS449F3hkVFLAdLyis dCY3hy22MNgyr+we4J6MFcicmiKFVlseVePV4fV1C3bYWO4i8rTqKBrO2qa76xl5pQsiHBaiQGWvJ ILlLU+Z0I4yPllHT1T8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWYGx-00DnDg-2b; Fri, 09 Sep 2022 07:17:55 +0000 Received: from mail-qk1-f169.google.com ([209.85.222.169]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWYGi-00DmSR-TP for linux-riscv@lists.infradead.org; Fri, 09 Sep 2022 07:17:42 +0000 Received: by mail-qk1-f169.google.com with SMTP id g13so564513qkm.4 for ; Fri, 09 Sep 2022 00:17:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date; bh=GbISm7ahSLrwT2Au2tPllsLxCWm8oBE76/YUTIUdxx0=; b=bF5Oa7QSpw0f46XK6AkXKm3tkZsVdqwRgP5MjVL15DABMAkMnG5xCPQKyyZRp8CL/d vp39OvR3bj10skaESyrNDH94aWvexjbHR6rivimFfQhufnbVL/iU+5D2KcuuBXHZy0JC jNlPCn8YUCDb1eX67f+++enCAFNPSbZwqYTW3KCf0UZgK0tYzZ29L4NB0o3dZY9adJcF 0kAwFrQEqH+EwM3iRngevDslUh2QM3YTqU5G1p9Guht5mEVix5/2u0Bskx9thNv1/PyA lpvRcArWdn1w4dWUqYADZEVREzutZgAxeeRqJK5eDXyEJUsqSYcg4LqOc6kMspxiMlhR C9QQ== X-Gm-Message-State: ACgBeo10l97afS3RrFh5d5XZfohBv8P+j55LLV04u9kD6nwm1/CAuLml hm2GYR/KeQiFlcexxtNB1+Ezt+/HLpN7FA== X-Google-Smtp-Source: AA6agR5ZhIyZymHrZzFTb6Y9imrmrD954SeiQvKkhKv0ySx2p4iuKRJHJnnO1aTRstP0jVqq9qnPCQ== X-Received: by 2002:a05:620a:25d0:b0:6bb:f597:1a3 with SMTP id y16-20020a05620a25d000b006bbf59701a3mr8977206qko.43.1662707855410; Fri, 09 Sep 2022 00:17:35 -0700 (PDT) Received: from mail-yb1-f179.google.com (mail-yb1-f179.google.com. [209.85.219.179]) by smtp.gmail.com with ESMTPSA id w16-20020ac87190000000b0034305a91aaesm1012249qto.83.2022.09.09.00.17.35 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 00:17:35 -0700 (PDT) Received: by mail-yb1-f179.google.com with SMTP id 130so1381401ybw.8 for ; Fri, 09 Sep 2022 00:17:35 -0700 (PDT) X-Received: by 2002:a25:3851:0:b0:6ad:9cba:9708 with SMTP id f78-20020a253851000000b006ad9cba9708mr8823957yba.36.1662707449504; Fri, 09 Sep 2022 00:10:49 -0700 (PDT) MIME-Version: 1.0 References: <20220815050815.22340-1-samuel@sholland.org> <20220815050815.22340-7-samuel@sholland.org> <20220815141159.10edeba5@donnerap.cambridge.arm.com> <3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com> <932aaefd-e2ca-ef26-bf30-e315fb271ec5@sholland.org> <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> <44b6f601-1a11-aacf-5592-5b61550afb9f@microchip.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 09:10:37 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree To: Samuel Holland Cc: Conor Dooley , Andre Przywara , Jessica Clarke , devicetree , Albert Ou , Linux Kernel Mailing List , Jernej Skrabec , "Lad, Prabhakar" , Chen-Yu Tsai , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv , linux-sunxi@lists.linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220909_001740_994569_0681A527 X-CRM114-Status: GOOD ( 36.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SGkgU2FtdWVsLAoKT24gRnJpLCBTZXAgOSwgMjAyMiBhdCA1OjQyIEFNIFNhbXVlbCBIb2xsYW5k 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