* [PATCH v2] clk: renesas: r9a07g044: Add TSU clock and reset entry
@ 2021-11-20 18:04 Biju Das
2021-11-23 11:25 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Biju Das @ 2021-11-20 18:04 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add TSU clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change, rebased to latest renesas-clk
---
drivers/clk/renesas/r9a07g044-cpg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index c0ca021136fa..a91ccad6329b 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -260,6 +260,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x5a8, 0),
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
0x5a8, 1),
+ DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
+ 0x5ac, 0),
};
static struct rzg2l_reset r9a07g044_resets[] = {
@@ -308,6 +310,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
+ DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] clk: renesas: r9a07g044: Add TSU clock and reset entry
2021-11-20 18:04 [PATCH v2] clk: renesas: r9a07g044: Add TSU clock and reset entry Biju Das
@ 2021-11-23 11:25 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2021-11-23 11:25 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On Sat, Nov 20, 2021 at 7:04 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add TSU clock and reset entry to CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2021-11-20 18:04 [PATCH v2] clk: renesas: r9a07g044: Add TSU clock and reset entry Biju Das
2021-11-23 11:25 ` Geert Uytterhoeven
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