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[209.85.217.49]) by smtp.gmail.com with ESMTPSA id o11sm315154vsl.0.2022.02.24.01.17.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Feb 2022 01:17:52 -0800 (PST) Received: by mail-vs1-f49.google.com with SMTP id g20so1414550vsb.9; Thu, 24 Feb 2022 01:17:52 -0800 (PST) X-Received: by 2002:a67:e10e:0:b0:31b:956b:70cf with SMTP id d14-20020a67e10e000000b0031b956b70cfmr644365vsl.77.1645694272225; Thu, 24 Feb 2022 01:17:52 -0800 (PST) MIME-Version: 1.0 References: <20220222103437.194779-1-miquel.raynal@bootlin.com> <20220222103437.194779-8-miquel.raynal@bootlin.com> <20220223181403.11744043@xps13> In-Reply-To: <20220223181403.11744043@xps13> From: Geert Uytterhoeven Date: Thu, 24 Feb 2022 10:17:41 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 7/8] ARM: dts: r9a06g032: Add the two DMA nodes To: Miquel Raynal Cc: Vinod Koul , Andy Shevchenko , dmaengine , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Magnus Damm , Gareth Williams , Phil Edworthy , Stephen Boyd , Michael Turquette , linux-clk , Thomas Petazzoni , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Hi Miquel, On Wed, Feb 23, 2022 at 6:14 PM Miquel Raynal wrote: > geert@linux-m68k.org wrote on Wed, 23 Feb 2022 13:54:20 +0100: > > On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal > > wrote: > > > Describe the two DMA controllers available on this SoC. > > > > > > Signed-off-by: Miquel Raynal > > > > Thanks for your patch! > > > > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > > @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { > > > status = "disabled"; > > > }; > > > > > > + dma0: dma-controller@40104000 { > > > + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; > > > + reg = <0x40104000 0x1000>; > > > + interrupts = ; > > > + clock-names = "hclk"; > > > + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; > > > > power-domains? > > > > > + dma-channels = <8>; > > > + dma-requests = <16>; > > > + dma-masters = <1>; > > > + #dma-cells = <3>; > > > > <4>? The dmamux bindings say: > > > > + The first four cells are dedicated to the master DMA > > controller. The fifth > > + cell gives the DMA mux bit index that must be set starting from 0. The > > + sixth cell gives the binary value that must be written there, ie. 0 or 1. > > The DMAC bindings had initially 3 cells, and then received a fourth > optional one. We do not need it here, that's why I'm keeping #dma-cells > to 3. > > But on the mux side, I don't want to deal with the presence or absence > of the optional cell so I assumed we would always request 4 cells for > the DMAC to be on the safe side. > > Is this assumption wrong? OK. Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds