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[209.85.128.180]) by smtp.gmail.com with ESMTPSA id d12-20020ac8060c000000b0039d085a2571sm219318qth.55.2022.11.17.03.20.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Nov 2022 03:20:33 -0800 (PST) Received: by mail-yw1-f180.google.com with SMTP id 00721157ae682-3691e040abaso15476707b3.9; Thu, 17 Nov 2022 03:20:33 -0800 (PST) X-Received: by 2002:a05:690c:b81:b0:37e:6806:a5f9 with SMTP id ck1-20020a05690c0b8100b0037e6806a5f9mr1541973ywb.47.1668684033193; Thu, 17 Nov 2022 03:20:33 -0800 (PST) MIME-Version: 1.0 References: <20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221107175305.63975-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221107175305.63975-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 17 Nov 2022 12:20:21 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 4/5] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts To: Prabhakar Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Prabhakar, On Mon, Nov 7, 2022 at 6:53 PM Prabhakar wrote: > From: Lad Prabhakar > > Add required properties in pinctrl node to handle GPIO interrupts. > > Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent > is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver > continues without waiting for IRQC to probe. > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi > @@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&pinctrl 0 0 152>; > + #interrupt-cells = <2>; > + interrupt-controller; > clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; > power-domains = <&cpg>; > resets = <&cpg R9A07G043_GPIO_RSTN>, > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > index 7a8ed7ae253b..65e7b029361e 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > @@ -98,6 +98,10 @@ &irqc { > resets = <&cpg R9A07G043_IA55_RESETN>; > }; > > +&pinctrl { > + interrupt-parent = <&irqc>; > +}; Do you plan to move it back to the common r9a07g043.dtsi later? Perhaps it makes sense to move the full irqc node to r9a07g043[uf].dtsi? There is not that much common left, even the compatible value differs. We don't keep the few common properties of the cpu0 node in r9a07g043.dtsi neither. > + > &soc { > interrupt-parent = <&gic>; > Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds