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[209.85.219.173]) by smtp.gmail.com with ESMTPSA id m21-20020a05620a24d500b006ce0733caebsm249240qkn.14.2022.11.17.02.54.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Nov 2022 02:54:07 -0800 (PST) Received: by mail-yb1-f173.google.com with SMTP id i131so1393529ybc.9; Thu, 17 Nov 2022 02:54:07 -0800 (PST) X-Received: by 2002:a5b:24b:0:b0:6ca:3b11:8d76 with SMTP id g11-20020a5b024b000000b006ca3b118d76mr1544397ybp.202.1668682446781; Thu, 17 Nov 2022 02:54:06 -0800 (PST) MIME-Version: 1.0 References: <20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221107175305.63975-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221107175305.63975-2-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 17 Nov 2022 11:53:55 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC To: Prabhakar Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Prabhakar, On Mon, Nov 7, 2022 at 6:53 PM Prabhakar wrote: > From: Lad Prabhakar > > Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is > identical to one found on the RZ/G2L SoC. No driver changes are > required as generic compatible string "renesas,rzg2l-irqc" will be > used as a fallback. > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- > Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five > - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt > domain) -> RISCV INTC I think this difference is purely a software difference, and abstracted in DTS through the interrupt hierarchy. Does it have any impact on the bindings? > - On the RZ/Five we have additional registers for IRQC block Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus warranting separate compatible values. > - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC Can you please elaborate? I may have missed something, but to me it looks like that is exactly the same on RZ/G2UL and on RZ/Five. > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > @@ -26,6 +26,7 @@ properties: > compatible: > items: > - enum: > + - renesas,r9a07g043u-irqc # RZ/G2UL > - renesas,r9a07g044-irqc # RZ/G2{L,LC} > - renesas,r9a07g054-irqc # RZ/V2L > - const: renesas,rzg2l-irqc Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds