From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E9C0C4332F for ; Tue, 22 Feb 2022 15:37:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231244AbiBVPiS (ORCPT ); Tue, 22 Feb 2022 10:38:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232110AbiBVPiR (ORCPT ); Tue, 22 Feb 2022 10:38:17 -0500 Received: from mail-vs1-f47.google.com (mail-vs1-f47.google.com [209.85.217.47]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56BCD9EB94; Tue, 22 Feb 2022 07:37:52 -0800 (PST) Received: by mail-vs1-f47.google.com with SMTP id d26so16777980vsh.0; Tue, 22 Feb 2022 07:37:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KBcpZ9jgJoMWEogAlgZ2QiXNeISgYGA0u6kHLE5F+0E=; b=0U2yZgBjwR3orXqm3oQZOipDgjYPiqo3z5FrqhPWQhyqfXid4gin6IlBFC9QDD29x8 l2t4J5TnfwvJ/2RY/fTeomw850eFD2w9cwMMmP5pDCl+WHX8MS8bIU0CH43GoN2Nyn+J vPbdzpxEZgFnHmpFInvoFQTBZslZ0aqOuIL2EJcQgqU/70pbytIY9IZZqR4D53WbMUx5 2szm7tJ6ycM7gclac21G+DebJYLlwsZSpdTKETUDMXh/ol31NM04PH46vo/x5QR8IvTf vEvL5tPkxwLsSf5DczAtep+42K+YrqkgY3kvJj/q7lmConThPv2Oh0Dzlv6NQ6NEDkss dPJA== X-Gm-Message-State: AOAM532lsMpovtlJWEtWzd/+zjE6q4/sr7HM6hNemxuJ6dnDyZC/bQ1t PDkSJRwy4iaLlpmrOi09CQ+i9XTR+HF/rw== X-Google-Smtp-Source: ABdhPJwAmY/e6ylaBrqzes2fn32Q/H1kwG8HLlK27FMstcqZra6HcZnKC/sW3SLOFLtCjuvB5mvjyw== X-Received: by 2002:a67:e005:0:b0:31b:74eb:1005 with SMTP id c5-20020a67e005000000b0031b74eb1005mr9092753vsl.50.1645544269870; Tue, 22 Feb 2022 07:37:49 -0800 (PST) Received: from mail-vk1-f179.google.com (mail-vk1-f179.google.com. [209.85.221.179]) by smtp.gmail.com with ESMTPSA id x144sm2633572vkx.22.2022.02.22.07.37.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Feb 2022 07:37:49 -0800 (PST) Received: by mail-vk1-f179.google.com with SMTP id f12so10598364vkl.2; Tue, 22 Feb 2022 07:37:49 -0800 (PST) X-Received: by 2002:a05:6122:114e:b0:32d:4662:65a8 with SMTP id p14-20020a056122114e00b0032d466265a8mr10537592vko.0.1645544269414; Tue, 22 Feb 2022 07:37:49 -0800 (PST) MIME-Version: 1.0 References: <6d8a6a05564f38f9d20464c1c17f96e52740cf6a.1645460429.git.geert+renesas@glider.be> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 22 Feb 2022 16:37:38 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] pinctrl: sh-pfc: checker: Fix miscalculation of number of states To: Linus Walleij Cc: Linux-Renesas , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Linus, On Tue, Feb 22, 2022 at 4:27 PM Linus Walleij wrote: > On Mon, Feb 21, 2022 at 5:22 PM Geert Uytterhoeven > wrote: > > The checker failed to validate all enum IDs in the description of a > > register with fixed-width register fields, due to a miscalculation of > > the number of described states: each register field of n bits can have > > "1 << n" possible states, not "1". > > > > Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked > > (SH-Mobile AG5 has more than 4000 enum IDs defined). > > > > Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts") > > Signed-off-by: Geert Uytterhoeven > > --- > > To be queued in renesas-pinctrl-for-v5.18. And obviously I should have done s/sh-pfc/renesas/ in the subject line. Will fix... > I certainly trust you to generally do what is best for the Renesas drivers. Thanks! > I have a question about this checker infrastructure because it is obviously > a piece of really valuable code for Renesas. > > How general is this checker? Do we have other drivers in the kernel that > would benefit from it or is it completely Renesas-specific? > > If it has general value I think it should be moved to be one floor down, > with the pinctrl framework, if possible. But I don't know the details. Unfortunately it is completely Renesas-specific, and relies on the way pins are configured in most (but not all) Renesas SoCs (both SH and ARM). I assume similar checks could be added to other pin control drivers, especially if they are using groups. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds