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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id br13-20020a05620a460d00b00680d020b4cbsm7111005qkb.10.2022.03.31.05.38.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Mar 2022 05:38:35 -0700 (PDT) Received: by mail-yw1-f173.google.com with SMTP id 00721157ae682-2e68c95e0f9so253028987b3.0; Thu, 31 Mar 2022 05:38:35 -0700 (PDT) X-Received: by 2002:a81:59c4:0:b0:2e5:c7c3:5d29 with SMTP id n187-20020a8159c4000000b002e5c7c35d29mr4667098ywb.512.1648730315185; Thu, 31 Mar 2022 05:38:35 -0700 (PDT) MIME-Version: 1.0 References: <20220315152717.20045-1-biju.das.jz@bp.renesas.com> <20220315152717.20045-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20220315152717.20045-2-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 31 Mar 2022 14:38:23 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/2] pinctrl: renesas: rzg2l: Add RZ/G2UL support To: Biju Das Cc: Linus Walleij , Linux-Renesas , "open list:GPIO SUBSYSTEM" , Chris Paterson , Biju Das , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Biju, On Tue, Mar 15, 2022 at 4:27 PM Biju Das wrote: > RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin > definitions are different compared to RZ/G2L. > > This patch adds a new compatible to take care of this differences > by adding r9a07g043_data with r9a07g043_gpio_configs and > rzg2l_dedicated_pins.common. > > Signed-off-by: Biju Das > Reviewed-by: Lad Prabhakar Thanks for your patch! > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, While the datasheet states QSPI_INT# has the VMC capability, it does not state that pin has the Slew Rate capability. Moreover, the QSPI_INT# functionality is not documented anywhere else in the datasheet (except for a (stale?) reference in the Boot Mode chapter), nor in the pinfunction spreadsheet. Hence it looks like that pin does not exist on RZ/G2UL, and thus should be moved to rzg2l_pins below. > + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, > + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, > + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, > + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, > + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, > + }, > + .rzg2l_pins = { > + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, > + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, > + } > }; The rest LGTM, so Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds