From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6C69C388F9 for ; Thu, 22 Oct 2020 14:09:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75EBB24182 for ; Thu, 22 Oct 2020 14:09:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2900688AbgJVOJh (ORCPT ); Thu, 22 Oct 2020 10:09:37 -0400 Received: from mail-ot1-f66.google.com ([209.85.210.66]:46485 "EHLO mail-ot1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2900678AbgJVOJg (ORCPT ); Thu, 22 Oct 2020 10:09:36 -0400 Received: by mail-ot1-f66.google.com with SMTP id m11so1567329otk.13; Thu, 22 Oct 2020 07:09:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qWi7olx0i8jeUc5svHxbdLLoehMJAACFeJtvJPwksLs=; b=TbKTaJNJyUE3xuyt9c+RFUDzi/fzDxpbvkg+Gd0HW4kDr+x/JtQEn1ATDy35BinY6I OgQ7JHOTf1HShQmVWyQ3uQUbM9SKZWzUjhIdYy7PE5MPCLmVVSq4WByn7UhA/oRIELtI z7lgGjdEg5IcDs7NGci8SYLzaFXawjNkVOISFfY7PwyVUUdp+ICIavHovIO/j3vO6BD/ H8aoEhGKH281K4TCvroGSi7VdLtfgWe4dGQ0DjCrOumnnZnGDMPcMZOLgEKe8m869m5F 9IKDCHb1UHeQ5Dvv2gqH9wxXyzD/9giJUvNN1p7PMxaciCQtDUzayA3pSTNC+pgkDOaN rZHw== X-Gm-Message-State: AOAM533aBZYhgcy7dJau4Ii9f3Tg2BZ8vo2e+8I3jrm2BJiKjXRKJ3TE gkEA9V0p8g+GQHADAEuiOdLe8BtTgy0kCr5kcvw= X-Google-Smtp-Source: ABdhPJyI/I2qD0HIY714dpAMocse+Wp7lpuhjH3pC+OK6EZ5BfvM4PxsL1QFGTV3yw9z+HQUyBUlrd1ttcwaiSXosyA= X-Received: by 2002:a05:6830:210a:: with SMTP id i10mr1979468otc.145.1603375775423; Thu, 22 Oct 2020 07:09:35 -0700 (PDT) MIME-Version: 1.0 References: <20201016121709.8447-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20201016121709.8447-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20201016121709.8447-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 22 Oct 2020 16:09:24 +0200 Message-ID: Subject: Re: [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks To: Lad Prabhakar Cc: Michael Turquette , Stephen Boyd , Linux-Renesas , linux-clk , Linux Kernel Mailing List , Biju Das , Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar wrote: > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR > driver. > > Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). > > Signed-off-by: Lad Prabhakar > Reviewed-by: Biju Das Thanks for your patch! > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { > DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), > + > + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, > + CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, > + R8A774C0_CLK_RPC), > > DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), > > @@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device *dev) > return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); > } > > +static const struct clk_div_table cpg_rpcsrc_div_table[] = { > + { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0}, > +}; The above models RPCSRC as a clock generated by dividing PLL1 by either 5, 3, 8, or 2. This does not match the hardware user's manual, which states that RPCSRC is either PLL1 divided by 5 or 3, or PLL0 divided by 8 or 2. I think you need a new clock type (CLK_TYPE_GEN3E_RPCSRC, as it applies to RZ/G2E, and R-Car E3?), which registers a composite clock consisting of a mux and divider. This is a bit similar to the RPC/RPCD2 clocks, which are composite clocks consisting of a divider and a gate. Note that R-Car D3 is similar, except that PLL0 is divided by 5 or 2, which means yet another clock type (and div_table). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds