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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id i19-20020ac84f53000000b002f3ca56e6edsm1078611qtw.8.2022.05.12.23.53.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 May 2022 23:53:50 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id x74so1068432ybe.4; Thu, 12 May 2022 23:53:49 -0700 (PDT) X-Received: by 2002:a25:c0d5:0:b0:64a:c6dd:1a00 with SMTP id c204-20020a25c0d5000000b0064ac6dd1a00mr3118805ybf.365.1652424829627; Thu, 12 May 2022 23:53:49 -0700 (PDT) MIME-Version: 1.0 References: <20220511183210.5248-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220511183210.5248-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 13 May 2022 08:53:38 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt To: "Lad, Prabhakar" Cc: Lad Prabhakar , Linus Walleij , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Bartosz Golaszewski , Philipp Zabel , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Phil Edworthy , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Prabhakar, On Thu, May 12, 2022 at 7:36 PM Lad, Prabhakar wrote: > On Thu, May 12, 2022 at 8:39 AM Geert Uytterhoeven wrote: > > On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar > > wrote: > > > Add IRQ domian to RZ/G2L pinctrl driver to handle GPIO interrupt. > > > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be > > > used as IRQ lines at given time. Selection of pins as IRQ lines > > > is handled by IA55 (which is the IRQC block) which sits in between the > > > GPIO and GIC. > > > > > > Signed-off-by: Lad Prabhakar > > > > Thanks for your patch! > > > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > > > > static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) > > > { > > > struct device_node *np = pctrl->dev->of_node; > > > struct gpio_chip *chip = &pctrl->gpio_chip; > > > const char *name = dev_name(pctrl->dev); > > > + struct irq_domain *parent_domain; > > > struct of_phandle_args of_args; > > > + struct device_node *parent_np; > > > + struct gpio_irq_chip *girq; > > > int ret; > > > > > > + parent_np = of_irq_find_parent(np); > > > + if (!parent_np) > > > + return -ENXIO; > > > + > > > + parent_domain = irq_find_host(parent_np); > > > + of_node_put(parent_np); > > > + if (!parent_domain) > > > + return -EPROBE_DEFER; > > > + > > > ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); > > > if (ret) { > > > dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); > > > @@ -1138,6 +1330,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) > > > chip->base = -1; > > > chip->ngpio = of_args.args[2]; > > > > > > + girq = &chip->irq; > > > + girq->chip = &rzg2l_gpio_irqchip; > > > + girq->fwnode = of_node_to_fwnode(np); > > > + girq->parent_domain = parent_domain; > > > + girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; > > > + girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; > > > + girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; > > > + girq->ngirq = RZG2L_TINT_MAX_INTERRUPT; > > > + > > > > I think you need to provide a .init_valid_mask() callback, as > > gpiochip_irqchip_remove() relies on that for destroying interrupts. > Are you suggesting the callback to avoid looping through all the GPIO pins? gpiochip_irqchip_remove() does: /* Remove all IRQ mappings and delete the domain */ if (gc->irq.domain) { unsigned int irq; for (offset = 0; offset < gc->ngpio; offset++) { if (!gpiochip_irqchip_irq_valid(gc, offset)) continue; irq = irq_find_mapping(gc->irq.domain, offset); irq_dispose_mapping(irq); } irq_domain_remove(gc->irq.domain); } The main thing is not about avoiding to loop through all GPIO pins, but to avoid irq_{find,dispose}_mapping() doing the wrong thing. The loop is over all GPIO offsets, while not all of them are mapped to valid interrupts. Does the above work correctly? > > However, the mask will need to be dynamic, as GPIO interrupts can be > > mapped and unmapped to one of the 32 available interrupts dynamically, > > right? > Yep that's correct. > > > I'm not sure if that can be done easily: if gpiochip_irqchip_irq_valid() > > is ever called too early, before the mapping is done, it would fail. > > > The mask initialization is a one time process and that is during > adding the GPIO chip. At this stage we won't be knowing what will be > the valid GPIO pins used as interrupts. Maybe the core needs to > implement a callback which lands in the GPIO controller driver to tell > if the gpio irq line is valid. This way we can handle dynamic > interrupts. Upon closer look, I think the mask is a red herring, and we don't need it. But we do need to handle the (possible) mismatch between GPIO offset (index) and IRQ offset in the above code. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds