Re: [PATCH 02/02] ARM: shmobile: marzen-reference: Remove IRLM workaround

[Geert Uytterhoeven <geert@linux-m68k.org>]

Hi Magnus,

On Thu, Dec 4, 2014 at 10:24 AM, Magnus Damm <magnus.damm@gmail.com> wrote:
> On Thu, Dec 4, 2014 at 6:19 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> On Thu, Dec 4, 2014 at 8:33 AM, Magnus Damm <magnus.damm@gmail.com> wrote:
>>>>> --- 0002/arch/arm/boot/dts/r8a7779.dtsi
>>>>> +++ work/arch/arm/boot/dts/r8a7779.dtsi       2014-12-03 20:27:49.000000000 +0900
>>>>> @@ -139,7 +139,7 @@
>>>>>               interrupt-controller;
>>>>>       };
>>>>>
>>>>> -     irqpin0: irqpin@fe780010 {
>>>>> +     irqpin0: irqpin@fe780000 {
>>>>>               compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
>>>>>               #interrupt-cells = <2>;
>>>>>               status = "disabled";
>>>>> @@ -148,7 +148,8 @@
>>>>>                       <0xfe780010 4>,
>>>>>                       <0xfe780024 4>,
>>>>>                       <0xfe780044 4>,
>>>>> -                     <0xfe780064 4>;
>>>>> +                     <0xfe780064 4>,
>>>>> +                     <0xfe780000 4>;
>>>>
>>>> Is there any order implied by the above list?
>>>> Naïvely I would expect it to be sorted numerically.
>>>
>>> Yes, the driver assumes the register banks to be passed in a certain
>>> order. In the case of r8a7779 we add one more register bank at the end
>>> for IRLM setup. Register detail (base address, access size, order and
>>> bitfield width) varies with SoC version. So the IRLM register will be
>>> at different addresses depending on SoC, but the driver wants it at
>>> the end of the list.
>>
>> As these are all individual registers, and there are that many, I think
>> it's worth adding a reg-names property to identify the registers.
>> Of course the driver still has to support the old anonymous order
>> for backwards compatibility.
>
> If we should rework things, then I propose going the other way around.
> =) Basically only passing a single base address with a certain SoC
> specific compat string, and based on that letting the driver
> internally figure out which register is at what offset and the access
> size and bitfield size.

That's gonna mean a complete new compatible value.
Seems like we shouldn't have added "renesas,intc-irqpin-r8a7779",
as the SoC-type was encoded in the reg properties...

> Either way we have a limited number of SoCs and they are all old.

So your current patch looks like the best option for now
(can you promise future R-Car SoCs won't have an intc-irqpin hardware
 block ;-)?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds