From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752511AbeDRJav (ORCPT ); Wed, 18 Apr 2018 05:30:51 -0400 Received: from mail-vk0-f68.google.com ([209.85.213.68]:45662 "EHLO mail-vk0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750983AbeDRJat (ORCPT ); Wed, 18 Apr 2018 05:30:49 -0400 X-Google-Smtp-Source: AIpwx4+rDGM9QEmU4Km4jOMa9DTOVOKZuxsPAzjfyyHyNmfnqzhWKRAvJ0NAeUwyJjtaHlTf4TYZ9RpgKkKEbpzLR0U= MIME-Version: 1.0 In-Reply-To: <20180416215032.5023-6-mylene.josserand@bootlin.com> References: <20180416215032.5023-1-mylene.josserand@bootlin.com> <20180416215032.5023-6-mylene.josserand@bootlin.com> From: Geert Uytterhoeven Date: Wed, 18 Apr 2018 11:30:47 +0200 X-Google-Sender-Auth: ydqY3PIRRw_LEGfhevbRqg9bAeU Message-ID: Subject: Re: [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF To: =?UTF-8?Q?Myl=C3=A8ne_Josserand?= Cc: Russell King , Maxime Ripard , Chen-Yu Tsai , Marc Zyngier , Mark Rutland , Rob Herring , Simon Horman , Magnus Damm , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LABBE Corentin , quentin.schulz@bootlin.com, Thomas Petazzoni , Linux ARM , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w3I9UtHn017962 Allo Mylène, On Mon, Apr 16, 2018 at 11:50 PM, Mylène Josserand wrote: > The CNTVOFF register from arch timer is uninitialized. > It should be done by the bootloader but it is currently not the case, > even for boot CPU because this SoC is booting in secure mode. > It leads to an random offset value meaning that each CPU will have a > different time, which isn't working very well. > > Add assembly code used for boot CPU and secondary CPU cores to make > sure that the CNTVOFF register is initialized. Because this code can > be used by different platforms, add this assembly file in ARM's common > folder. Thanks for your patch! > Signed-off-by: Mylène Josserand Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 From: geert@linux-m68k.org (Geert Uytterhoeven) Date: Wed, 18 Apr 2018 11:30:47 +0200 Subject: [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF In-Reply-To: <20180416215032.5023-6-mylene.josserand@bootlin.com> References: <20180416215032.5023-1-mylene.josserand@bootlin.com> <20180416215032.5023-6-mylene.josserand@bootlin.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Allo Myl?ne, On Mon, Apr 16, 2018 at 11:50 PM, Myl?ne Josserand wrote: > The CNTVOFF register from arch timer is uninitialized. > It should be done by the bootloader but it is currently not the case, > even for boot CPU because this SoC is booting in secure mode. > It leads to an random offset value meaning that each CPU will have a > different time, which isn't working very well. > > Add assembly code used for boot CPU and secondary CPU cores to make > sure that the CNTVOFF register is initialized. Because this code can > be used by different platforms, add this assembly file in ARM's common > folder. Thanks for your patch! > Signed-off-by: Myl?ne Josserand Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds