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[209.85.219.177]) by smtp.gmail.com with ESMTPSA id d187-20020a37b4c4000000b0071f636c108bsm1732180qkf.73.2023.01.30.02.05.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jan 2023 02:05:49 -0800 (PST) Received: by mail-yb1-f177.google.com with SMTP id a9so13327154ybb.3; Mon, 30 Jan 2023 02:05:48 -0800 (PST) X-Received: by 2002:a25:9801:0:b0:7d5:b884:3617 with SMTP id a1-20020a259801000000b007d5b8843617mr4330104ybo.380.1675073148543; Mon, 30 Jan 2023 02:05:48 -0800 (PST) MIME-Version: 1.0 References: <20230127174014.251539-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 30 Jan 2023 11:05:36 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node To: Biju Das Cc: "Lad, Prabhakar" , Magnus Damm , Rob Herring , Krzysztof Kozlowski , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 27, 2023 at 10:48 PM Biju Das wrote: > > Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node > > On Fri, Jan 27, 2023 at 6:38 PM Biju Das wrote: > > > > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU > > > > node > > > > > > > > From: Lad Prabhakar > > > > > > > > Enable the performance monitor unit for the Cortex-A55 cores on the > > > > RZ/G2L > > > > (r9a07g044) SoC. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > --- > > > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++ > > > > 1 file changed, 5 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > index 80b2332798d9..ff9bdc03a3ed 100644 > > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > @@ -161,6 +161,11 @@ opp-50000000 { > > > > }; > > > > }; > > > > > > > > + pmu_a55 { > > > > + compatible = "arm,cortex-a55-pmu"; > > > > + interrupts-extended = <&gic GIC_PPI 7 > > > > + IRQ_TYPE_LEVEL_HIGH>; > > > > > > Just a question, Is it tested? > > Yes this was tested with perf test > > > > > timer node[1] defines irq type as LOW, here it is high. > > You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this should > > be LOW. (I followed the SPI IRQS where all the LEVEL interrupts are HIGH) > > > > > Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as > > it has 2 cores?? > > > > > No this is not required for example here [0] where it has 6 cores. > > I may be wrong, That is the only example[1], where the A55 PMU per cpu interrupts and number of a55 cores in the DT > are not matching. > > [1] > https://elixir.bootlin.com/linux/latest/B/ident/arm%2Ccortex-a55-pmu Indeed, this looks like an omission, propagated through arch/arm64/boot/dts/renesas/r8a779[afg]0.dtsi. And doesn't this apply to all PPI interrupts, i.e. shouldn't the GIC in arch/arm64/boot/dts/renesas/r9a07g0{43u,44u,54}.dtsi specify the mask in their interrupts properties, too? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds