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* [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
@ 2021-07-28 23:45 Linus Walleij
  2021-07-29  5:25 ` Krzysztof Hałasa
  2021-07-29 12:16 ` Geert Uytterhoeven
  0 siblings, 2 replies; 6+ messages in thread
From: Linus Walleij @ 2021-07-28 23:45 UTC (permalink / raw)
  To: linux-arm-kernel, Imre Kaloz, Krzysztof Halasa
  Cc: Linus Walleij, openwrt-devel

This is an example of how I think the Goramo MultiLink device can
be supported in the device tree.

It requires writing a new 74hc4094 GPIO driver and moving a bunch
of the boardfile code into the HSS driver as it is anyways the only
user of this facility. If there are other boards supporting HSS they
can be added too.

To proceed with this I need to be sure someone is willing to test
and help develop this and has interest in supporting the Goramo
MultiLink with recent kernels on e.g. OpenWrt.

I am happy to dry-code most of the code and DT bindings but it
needs to be tested and debugged on target.

I am also willing to write just the device tree bindings so the
device tree can be merged and the implementation be filled in
later. As long as I know there is active interest I'm willing to
do at least this even if it cannot be tested just to have the base
in place.

So is someone up for it? Krysztof?

If not, the boardfile will be deleted as part of the IXP4xx
migration to device tree, yet this shows how to bring it back.

Cc: openwrt-devel@lists.openwrt.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/boot/dts/Makefile                    |   1 +
 .../dts/intel-ixp42x-goramo-multilink.dts     | 201 ++++++++++++++++++
 arch/arm/boot/dts/intel-ixp4xx.dtsi           |  17 ++
 3 files changed, 219 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ac8a4a77584d..2dfb073b31a7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,6 +247,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
 	intel-ixp46x-ixdp465.dtb \
 	intel-ixp42x-adi-coyote.dtb \
 	intel-ixp42x-ixdpg425.dtb \
+	intel-ixp42x-goramo-multilink.dtb \
 	intel-ixp42x-iomega-nas100d.dtb \
 	intel-ixp42x-dlink-dsm-g600.dtb \
 	intel-ixp42x-gateworks-gw2348.dtb \
diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
new file mode 100644
index 000000000000..bd9a17fb2837
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Goramo MultiLink Router
+ * There are two variants:
+ * - MultiLink Basic (a box)
+ * - MultiLink Max (19" rack mount)
+ * This device tree supports MultiLink Basic.
+ * This machine is based on IXP425.
+ * This is one of the few devices supporting the IXP4xx High-Speed Serial
+ * (HSS) link for a V.35 WAN interface.
+ * The hardware seems to originate in Poland.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Goramo MultiLink Router";
+	compatible = "goramo,multilink-router", "intel,ixp42x";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory@0 {
+		/*
+		 * 64 MB of RAM according to the manual. The MultiLink
+		 * Max has 128 MB.
+		 */
+		device_type = "memory";
+		reg = <0x00000000 0x4000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+		stdout-path = "uart0:115200n8";
+	};
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	/*
+	 * 74HC4094 which is used as a rudimentary GPIO expander
+	 * FIXME:
+	 * - Create device tree bindings for this as GPIO expander
+	 * - Write a pure DT GPIO driver using these bindings
+	 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
+	 */
+	gpio_74: gpio-74hc4094 {
+		compatible = "nxp,74hc4094";
+		cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+		d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+		str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+		/* oe-gpios is optional */
+		gpio-controller;
+		#gpio-cells = <2>;
+		/* We are not cascaded */
+		registers-number = <1>;
+		gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
+				"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
+				"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
+	};
+
+	soc {
+		bus@c4000000 {
+			flash@0,0 {
+				compatible = "intel,ixp4xx-flash", "cfi-flash";
+				bank-width = <2>;
+				/* Enable writes on the expansion bus */
+				intel,ixp4xx-eb-write-enable = <1>;
+				/* 16 MB of Flash mapped in at CS0 */
+				reg = <0 0x00000000 0x1000000>;
+
+				partitions {
+					compatible = "redboot-fis";
+					/* Eraseblock at 0x0fe0000 */
+					fis-index-block = <0x7f>;
+				};
+			};
+		};
+
+		pci@c0000000 {
+			status = "ok";
+
+			/*
+			 * The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
+			 * The slots have Ethernet, Ethernet, NEC and MPCI.
+			 * The IDSELs are 11, 12, 13, 14.
+			 */
+			interrupt-map =
+			/* IDSEL 11 - Ethernet A */
+			<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
+			<0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
+			<0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
+			<0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
+			/* IDSEL 12 - Ethernet B */
+			<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
+			<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
+			<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
+			<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
+			/* IDSEL 13 - MPCI */
+			<0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
+			<0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
+			<0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
+			<0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
+			/* IDSEL 14 - NEC */
+			<0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
+			<0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
+			<0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
+			<0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
+		};
+
+		/*
+		 * The Goramo MultiLink Router uses different txready queues than any other router,
+		 * which makes it likely that it uses non-default firmware for the NPE units.
+		 */
+
+		/*
+		 * HSS links
+		 * FIXME:
+		 * - Device tree bindings
+		 * - Code to probe the HSS from device tree and get all queues and NPE from DT
+		 * - Put the boardfile code handling the GPIOs into the HSS driver
+		 */
+		npe@c8006000 {
+			hss@0 {
+				status = "okay";
+				queue-chl-rxtrig = <&qmgr 12>;
+				queue-pkt-rx = <&qmgr 13>;
+				queue-pkt-tx0 = <&qmgr 14>;
+				queue-pkt-tx1 = <&qmgr 15>;
+				queue-pkt-tx2 = <&qmgr 16>;
+				queue-pkt-tx3 = <&qmgr 17>;
+				queue-pkt-rxfree0 = <&qmgr 18>;
+				queue-pkt-rxfree1 = <&qmgr 19>;
+				queue-pkt-rxfree2 = <&qmgr 20>;
+				queue-pkt-rxfree3 = <&qmgr 21>;
+				queue-pkt-txdone = <&qmgr 22>;
+				/* The Goramo GPIO-based clock etc control */
+				cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+				rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+				dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+				dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
+				clk-int-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
+			};
+			hss@1 {
+				status = "okay";
+				queue-chl-rxtrig = <&qmgr 10>;
+				queue-pkt-rx = <&qmgr 0>;
+				queue-pkt-tx0 = <&qmgr 5>;
+				queue-pkt-tx1 = <&qmgr 6>;
+				queue-pkt-tx2 = <&qmgr 7>;
+				queue-pkt-tx3 = <&qmgr 8>;
+				queue-pkt-rxfree0 = <&qmgr 1>;
+				queue-pkt-rxfree1 = <&qmgr 2>;
+				queue-pkt-rxfree2 = <&qmgr 3>;
+				queue-pkt-rxfree3 = <&qmgr 4>;
+				queue-pkt-txdone = <&qmgr 9>;
+				/* The Goramo GPIO-based clock etc control */
+				cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+				rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+				dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+				dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
+				clk-int-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
+			};
+		};
+
+		/* EthB */
+		ethernet@c8009000 {
+			status = "ok";
+			queue-rx = <&qmgr 3>;
+			queue-txready = <&qmgr 32>;
+			phy-mode = "rgmii";
+			phy-handle = <&phy0>;
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				phy0: ethernet-phy@0 {
+					reg = <0>;
+				};
+
+				phy1: ethernet-phy@1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		/* EthC */
+		ethernet@c800a000 {
+			status = "ok";
+			queue-rx = <&qmgr 4>;
+			queue-txready = <&qmgr 33>;
+			phy-mode = "rgmii";
+			phy-handle = <&phy1>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index e5af2d463074..a490b70b8d93 100644
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -141,6 +141,23 @@ timer@c8005000 {
 		npe: npe@c8006000 {
 			compatible = "intel,ixp4xx-network-processing-engine";
 			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* NPE-A contains two high-speed serial links */
+			hss@0 {
+				compatible = "intel,ixp4xx-hss";
+				reg = <0>;
+				intel,npe-handle = <&npe 0>;
+				status = "disabled";
+			};
+
+			hss@1 {
+				compatible = "intel,ixp4xx-hss";
+				reg = <1>;
+				intel,npe-handle = <&npe 0>;
+				status = "disabled";
+			};
 
 			/* NPE-C contains a crypto accelerator */
 			crypto {
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
  2021-07-28 23:45 [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree Linus Walleij
@ 2021-07-29  5:25 ` Krzysztof Hałasa
  2021-07-29 11:31   ` Linus Walleij
  2021-07-29 12:16 ` Geert Uytterhoeven
  1 sibling, 1 reply; 6+ messages in thread
From: Krzysztof Hałasa @ 2021-07-29  5:25 UTC (permalink / raw)
  To: Linus Walleij; +Cc: linux-arm-kernel, Imre Kaloz, openwrt-devel

Hi Linus,

First, thanks for your continued work on those old platforms.

I'm not exactly sure how to proceed.

> It requires writing a new 74hc4094 GPIO driver and moving a bunch
> of the boardfile code into the HSS driver as it is anyways the only
> user of this facility. If there are other boards supporting HSS they
> can be added too.

I'm not aware of any other supported hw using HSS.

The 74HC4094... I appears it's used mostly for HSS (optional signals
depending on the hardware port version), but one of it's outputs drives
PCI reset as well. There is also /write-protect for a couple of serial
EEPROMs (one of them usually not installed). AFAIR the EEPROMs were
never used for anything, but were available for some custom sw etc.
Also, the EEPROM(s) should be functional without driving 74HC4094, they
would only be unprotected (the protection wouldn't be needed in
practically all cases anyway).

> To proceed with this I need to be sure someone is willing to test
> and help develop this and has interest in supporting the Goramo
> MultiLink with recent kernels on e.g. OpenWrt.

TBH, the last time I was running such a device it was using a kernel
within something like 3.1x range. I *think* I still have some of the
hardware (definitely not all types, but perhaps one of the later
versions). Also, I think I should have some serial sync hardware, so in
theory both the DTS conversion and the HSS operation could be tested.

OTOH I don't know if it's worth the effort. But, since you already wrote
the DTS file, perhaps it's better to just leave it in place (knowing
that certain functionality of certain versions will be unavailable). If
I can test and possibly fix something here, I will try to.

The following is:
Acked-by: Krzysztof Hałasa <khalasa@piap.pl>

Some notes:

> +++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: ISC
> +/*
> + * Device Tree file for the Goramo MultiLink Router
> + * There are two variants:
> + * - MultiLink Basic (a box)
> + * - MultiLink Max (19" rack mount)

The Max was usually not 19" rack version, it's the same circa 10" plastic
box as the basic (base?). The 19" case was available independently of
the router hw version (well, not for "micro" version).

As I remember it:
- there was MultiLink Micro: a small router module mounted inside
  a DSL-class modem. At least 2 versions, with small differences (maybe
  number of Ethernet ports or something like this). 32 MB of RAM, the
  latter were using (I think) 64 MB. HSS V.35 connector, the other HSS
  was used by the modem. No PCI, no USB.

- Basic: it had 64 MB of RAM. Standalone plastic box. 2 10/100 Ethernets
  (built-in, using LXT971 phy - in newer versions (v. 2.x) 2 additional
  optional Intel PCI 10/100 Mbps Ethernets). 2 HSS ports (usually V.35
  but could be configured, in hardware, as - I imagine - X.21, and even
  as T1 or E1 with additional PHY).

- Max: Basic on steroids. 128 MB of RAM (optionally 256 MB), mini PCI
  slot (mostly for WiFi).
  Original version: NEC USB 2.0 host controller (2 ports).
  Newer versions: IDE (PATA) connector, 4 USB 2.0 ports, all provided by
  a CS5536 ("Geode compation chip"). I *think* Basic version lacked this
  CS5536 (and Basic v. 1.0 lacked NEC USB). Also 2 Intel PCI Gigabit
  Ethernets.

All of those hw details were described in a config record in the flash.

> + * This device tree supports MultiLink Basic.
> + * This machine is based on IXP425.
> + * This is one of the few devices supporting the IXP4xx High-Speed Serial
> + * (HSS) link for a V.35 WAN interface.
> + * The hardware seems to originate in Poland.

s/seems to originate/originated/ :-)

> +		/*
> +		 * The Goramo MultiLink Router uses different txready queues than any other router,
> +		 * which makes it likely that it uses non-default firmware for the NPE units.
> +		 */

It used standard firmware, the txready queue # was configurable in
software. I guess it was different from other boards to avoid some
conflict with HSS.
IIRC the queue numbers changed at some point with firmware version.
But all those boards (not only Goramo MultiLinks but generally all
IXP4xx) were supposed to use the last firmware available.
-- 
Krzysztof "Chris" Hałasa

Sieć Badawcza Łukasiewicz
Przemysłowy Instytut Automatyki i Pomiarów PIAP
Al. Jerozolimskie 202, 02-486 Warszawa

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
  2021-07-29  5:25 ` Krzysztof Hałasa
@ 2021-07-29 11:31   ` Linus Walleij
  2021-07-30  5:26     ` Krzysztof Hałasa
  0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2021-07-29 11:31 UTC (permalink / raw)
  To: Krzysztof Hałasa; +Cc: Linux ARM, Imre Kaloz, OpenWrt Development List

On Thu, Jul 29, 2021 at 7:25 AM Krzysztof Hałasa <khalasa@piap.pl> wrote:

> OTOH I don't know if it's worth the effort. But, since you already wrote
> the DTS file, perhaps it's better to just leave it in place (knowing
> that certain functionality of certain versions will be unavailable). If
> I can test and possibly fix something here, I will try to.
>
> The following is:
> Acked-by: Krzysztof Hałasa <khalasa@piap.pl>

Let's say I write the DT bindings as well so that the device tree file
is valid, and then we can work on the implementation when there
is time. Does this work for you? I think the device tree will boot the
device fine, just that the HSS will not work until we implement the
GPIO and control code in the HSS driver.

Yours,
Linus Walleij

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
  2021-07-28 23:45 [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree Linus Walleij
  2021-07-29  5:25 ` Krzysztof Hałasa
@ 2021-07-29 12:16 ` Geert Uytterhoeven
  2021-08-11  9:08   ` Linus Walleij
  1 sibling, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2021-07-29 12:16 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Linux ARM, Imre Kaloz, Krzysztof Halasa, OpenWrt Development List

Hi Linus,

On Thu, Jul 29, 2021 at 1:54 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> This is an example of how I think the Goramo MultiLink device can
> be supported in the device tree.
>
> It requires writing a new 74hc4094 GPIO driver and moving a bunch
> of the boardfile code into the HSS driver as it is anyways the only
> user of this facility. If there are other boards supporting HSS they
> can be added too.

Can't the existing drivers/gpio/gpio-74x164.c be used?
See also Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
  2021-07-29 11:31   ` Linus Walleij
@ 2021-07-30  5:26     ` Krzysztof Hałasa
  0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Hałasa @ 2021-07-30  5:26 UTC (permalink / raw)
  To: Linus Walleij; +Cc: Linux ARM, Imre Kaloz, OpenWrt Development List

Linus Walleij <linus.walleij@linaro.org> writes:

> Let's say I write the DT bindings as well so that the device tree file
> is valid, and then we can work on the implementation when there
> is time. Does this work for you? I think the device tree will boot the
> device fine, just that the HSS will not work until we implement the
> GPIO and control code in the HSS driver.

Sure it's fine for me. Thanks for your work, again.
-- 
Krzysztof "Chris" Hałasa

Sieć Badawcza Łukasiewicz
Przemysłowy Instytut Automatyki i Pomiarów PIAP
Al. Jerozolimskie 202, 02-486 Warszawa

_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree
  2021-07-29 12:16 ` Geert Uytterhoeven
@ 2021-08-11  9:08   ` Linus Walleij
  0 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2021-08-11  9:08 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Linux ARM, Imre Kaloz, Krzysztof Halasa, OpenWrt Development List

On Thu, Jul 29, 2021 at 2:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Hi Linus,
(...)
> Can't the existing drivers/gpio/gpio-74x164.c be used?
> See also Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml

Sadly no. The way this device is used for GPIO is very
different. The former used a version of SPI and this has
to hammer GPIO lines directly, and has to use a special
strobe signal to propagate values out to pins.

Yours,
Linus Walleij

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^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-08-11  9:35 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-28 23:45 [PATCH] RFC: ARM: dts: Proposed Goramo MultiLink device tree Linus Walleij
2021-07-29  5:25 ` Krzysztof Hałasa
2021-07-29 11:31   ` Linus Walleij
2021-07-30  5:26     ` Krzysztof Hałasa
2021-07-29 12:16 ` Geert Uytterhoeven
2021-08-11  9:08   ` Linus Walleij

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