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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id br38-20020a05620a462600b006bbc09af9f5sm10390363qkb.101.2022.08.22.05.31.53 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Aug 2022 05:31:54 -0700 (PDT) Received: by mail-yw1-f173.google.com with SMTP id 00721157ae682-33365a01f29so288661177b3.2 for ; Mon, 22 Aug 2022 05:31:53 -0700 (PDT) X-Received: by 2002:a5b:6c1:0:b0:669:a7c3:4c33 with SMTP id r1-20020a5b06c1000000b00669a7c34c33mr18348478ybq.543.1661171513514; Mon, 22 Aug 2022 05:31:53 -0700 (PDT) MIME-Version: 1.0 References: <20220815050815.22340-1-samuel@sholland.org> <20220815050815.22340-7-samuel@sholland.org> <20220815141159.10edeba5@donnerap.cambridge.arm.com> <3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com> <932aaefd-e2ca-ef26-bf30-e315fb271ec5@sholland.org> <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> In-Reply-To: <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> From: Geert Uytterhoeven Date: Mon, 22 Aug 2022 14:31:41 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree To: Conor Dooley Cc: Andre Przywara , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Albert Ou , Samuel Holland , Linux Kernel Mailing List , Jernej Skrabec , "Lad, Prabhakar" , Chen-Yu Tsai , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv , linux-sunxi@lists.linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220822_053156_351368_3BADEF26 X-CRM114-Status: GOOD ( 34.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SGkgQ29ub3IsCgpPbiBNb24sIEF1ZyAyMiwgMjAyMiBhdCAyOjEzIFBNIDxDb25vci5Eb29sZXlA bWljcm9jaGlwLmNvbT4gd3JvdGU6Cj4gT24gMjIvMDgvMjAyMiAxMjo0NiwgR2VlcnQgVXl0dGVy aG9ldmVuIHdyb3RlOgo+ID4gT24gU3VuLCBBdWcgMjEsIDIwMjIgYXQgMTI6MDcgUE0gPENvbm9y LkRvb2xleUBtaWNyb2NoaXAuY29tPiB3cm90ZToKPiA+PiBPbiAyMS8wOC8yMDIyIDA3OjQ1LCBJ Y2Vub3d5IFpoZW5nIHdyb3RlOgo+ID4+PiDlnKggMjAyMi0wOC0yMOaYn+acn+WFreeahCAxNzoy OSArMDAwMO+8jENvbm9yLkRvb2xleUBtaWNyb2NoaXAuY29t5YaZ6YGT77yaCj4gPj4+PiBPbiAy MC8wOC8yMDIyIDE4OjI0LCBTYW11ZWwgSG9sbGFuZCB3cm90ZToKPgo+ID4+Pj4+IFRoaXMgaXMg bm90IGZlYXNpYmxlLCBkdWUgdG8gdGhlIGRpZmZlcmVudCAjaW50ZXJydXB0LWNlbGxzLiBTZWUK PiA+Pj4+PiBodHRwczovL2xvcmUua2VybmVsLm9yZy9saW51eC1yaXNjdi9DQU11SE1kWEhTTWNy Vk9IK3ZjcmRSUkYraTJUa01jRmlzR3hITUJQVUVhOG5UTUZwendAbWFpbC5nbWFpbC5jb20vCj4g Pj4+Pj4KPiA+Pj4+PiBFdmVuIGlmIHdlIHNoYXJlIHNvbWUgZmlsZSBhY3Jvc3MgYXJjaGl0ZWN0 dXJlcywgeW91IHN0aWxsIGhhdmUgdG8KPiA+Pj4+PiB1cGRhdGUgZmlsZXMKPiA+Pj4+PiBpbiBi b3RoIHBsYWNlcyB0byBnZXQgdGhlIGludGVycnVwdHMgcHJvcGVydGllcyBjb3JyZWN0Lgo+ID4+ Pj4+Cj4gPj4+Pj4gSSBnZXQgdGhlIGRlc2lyZSB0byBkZWR1cGxpY2F0ZSB0aGluZ3MsIGJ1dCB3 ZSBhbHJlYWR5IGRlYWwgd2l0aAo+ID4+Pj4+IHVwZGF0aW5nIHRoZQo+ID4+Pj4+IHNhbWUvc2lt aWxhciBub2RlcyBhY3Jvc3Mgc2V2ZXJhbCBTb0NzLCBzbyB0aGF0IGlzIG5vdGhpbmcgbmV3LiBJ Cj4gPj4+Pj4gdGhpbmsgaXQgd291bGQKPiA+Pj4+PiBiZSBtb3JlIGNvbmZ1c2luZy9jb21wbGlj YXRlZCB0byBoYXZlIGFsbCBvZiB0aGUgaW50ZXJydXB0cwo+ID4+Pj4+IHByb3BlcnRpZXMKPiA+ Pj4+PiBvdmVycmlkZGVuIGluIGEgc2VwYXJhdGUgZmlsZS4KPiA+Pj4+Cj4gPj4+PiBZZWFoLCBz aG91bGQgbWF5YmUgaGF2ZSBjaXJjbGVkIGJhY2sgYWZ0ZXIgdGhhdCBjb252ZXJzYXRpb24sIHdv dWxkCj4gPj4+PiBoYXZlIGJlZW4KPiA+Pj4+IG5pY2UgYnV0IGlmIHRoZSBEVEMgY2FuJ3QgZG8g aXQgbmljZWx5IHRoZW4gdy9lLgo+ID4+Pgo+ID4+PiBXZWxsLCBtYXliZSB3ZSBjYW4gb3ZlcnVz ZSB0aGUgZmFjaWxpdHkgb2YgQyBwcmVwcm9jZXNzb3I/Cj4gPj4+Cj4gPj4+IGUuZy4KPiA+Pj4K PiA+Pj4gYGBgCj4gPj4+IC8vIEZvciBBUk0KPiA+Pj4gI2RlZmluZSBTT0NfUEVSSVBIRVJBTF9J UlEobikgR0lDX1NQSSBuCj4gPj4+IC8vIEZvciBSSVNDLVYKPiA+Pj4gI2RlZmluZSBTT0NfUEVS SVBIRVJBTF9JUlEobikgbgo+ID4+PiBgYGAKPiA+Pj4KPiA+Pgo+ID4+IEdlZXJ0IHBvaW50ZWQg b3V0IHRoYXQgdGhpcyBpcyBub3QgcG9zc2libGUgKGF0IGxlYXN0IG9uIHRoZSBSZW5lc2FzCj4g Pj4gc3R1ZmYpIGJlY2F1c2UgdGhlIEdJQyBpbnRlcnJ1cHQgbnVtYmVycyBhcmUgbm90IHRoZSBz YW1lIGFzIHRoZQo+ID4+IFBMSUMncyAmIHRoZSBEVEMgaXMgbm90IGFibGUgdG8gaGFuZGxlIHRo ZSBhZGRpdGlvbjoKPiA+PiBodHRwczovL2xvcmUua2VybmVsLm9yZy9saW51eC1yaXNjdi9DQU11 SE1kWEhTTWNyVk9IK3ZjcmRSUkYraTJUa01jRmlzR3hITUJQVUVhOG5UTUZwendAbWFpbC5nbWFp bC5jb20vCj4gPgo+ID4gV2l0aG91dCB0aGUgYWJpbGl0eSB0byBkbyBhZGRpdGlvbnMgaW4gRFRD LCB3ZSBjb3VsZCBlLmcuIGxpc3QgYm90aAo+ID4gaW50ZXJydXB0cyBpbiB0aGUgbWFjcm8sIGxp a2U6Cj4gPgo+ID4gICAgICAvLyBGb3IgQVJNCj4gPiAgICAgICNkZWZpbmUgU09DX1BFUklQSEVS QUxfSVJRKG5hLCBucikgR0lDX1NQSSBuYQo+ID4gICAgICAvLyBGb3IgUklTQy1WCj4gPiAgICAg ICNkZWZpbmUgU09DX1BFUklQSEVSQUxfSVJRKG5hLCBucikgbnIKPgo+IERvIHlvdSB0aGluayB0 aGlzIGlzIHdvcnRoIGRvaW5nPyBPciBhcmUgeW91IGp1c3QgcHJvdmlkaW5nIGFuCj4gZXhhbXBs ZSBvZiB3aGF0IGNvdWxkIGJlIGRvbmU/CgpKdXN0IHNvbWUgYnJhaW5zdG9ybWluZy4uLgoKPiBX aGVyZSB3b3VsZCB5b3UgZW52aXNhZ2UgcHV0dGluZyB0aGVzZSBtYWNyb3M/IEkgZm9yZ2V0IHRo ZSBvcmRlcgo+IG9mIHRoZSBDUFAgb3BlcmF0aW9ucyB0aGF0IGFyZSBkb25lLCBjYW4gdGhleSBi ZSBwdXQgaW4gdGhlIGR0cz8KClRoZSBTT0NfUEVSSVBIRVJBTF9JUlEoKSBtYWNybyBzaG91bGQg YmUgZGVmaW5lZCBpbiB0aGUKQVJNLWJhc2VkIFNvQy5kdHNpIGZpbGUgYW5kIHRoZSBSSVNDLVYt YmFzZWQgU29DLmR0c2kgZmlsZS4KCj4gPiBPbiBNb24sIEF1ZyAyMiwgMjAyMiBhdCAxMjo1MiBQ TSBBbmRyZSBQcnp5d2FyYSA8YW5kcmUucHJ6eXdhcmFAYXJtLmNvbT4gd3JvdGU6Cj4gPj4gVGhl cmUgYXJlIGludGVycnVwdC1tYXBzIGZvciB0aGF0Ogo+ID4+IHN1bjhpLXI1MjguZHRzaToKPiA+ PiAgICAgICAgICBzb2Mgewo+ID4+ICAgICAgICAgICAgICAgICAgI2ludGVycnVwdC1jZWxscyA9 IDwxPjsKPiA+PiAgICAgICAgICAgICAgICAgIGludGVycnVwdC1tYXAgPSA8MCAgMTggJmdpYyBH SUNfU1BJICAyIElSUV9UWVBFX0xFVkVMX0hJR0g+LAo+ID4+ICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIDwwICAxOSAmZ2ljIEdJQ19TUEkgIDMgSVJRX1RZUEVfTEVWRUxfSElHSD4s Cj4gPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgLi4uLgo+ID4+Cj4gPj4gc3Vu MjBpLWQxLmR0c2k6Cj4gPj4gICAgICAgICAgc29jIHsKPiA+PiAgICAgICAgICAgICAgICAgICNp bnRlcnJ1cHQtY2VsbHMgPSA8MT47Cj4gPj4gICAgICAgICAgICAgICAgICBpbnRlcnJ1cHQtbWFw ID0gPDAgIDE4ICZwbGljICAxOCBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKPiA+PiAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICA8MCAgMTkgJnBsaWMgIDE5IElSUV9UWVBFX0xFVkVMX0hJ R0g+LAo+ID4+Cj4gPj4gdGhlbiwgaW4gdGhlIHNoYXJlZCAuZHRzaToKPiA+PiAgICAgICAgICAg ICAgICAgIHVhcnQwOiBzZXJpYWxAMjUwMDAwMCB7Cj4gPj4gICAgICAgICAgICAgICAgICAgICAg ICAgIGNvbXBhdGlibGUgPSAic25wcyxkdy1hcGItdWFydCI7Cj4gPj4gICAgICAgICAgICAgICAg ICAgICAgICAgIC4uLgo+ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0g PDE4PjsKPiA+Cj4gPiBOaWNlISBCdXQgaXQncyBnb25uYSBiZSBhIHZlcnkgbGFyZ2UgaW50ZXJy dXB0LW1hcC4KPgo+IEkgcXVpdGUgbGlrZSB0aGUgaWRlYSBvZiBub3QgZHVwbGljYXRpbmcgZmls ZXMgYWNyb3NzIHRoZSBhcmNocwo+IGlmIGl0IGNhbiBiZSBoZWxwZWQsIGJ1dCBub3QgYXQgdGhl IGV4cGVuc2Ugb2YgbWFraW5nIHRoZW0gaGFyZCB0bwo+IHVuZGVyc3RhbmQgJiBJIGZlZWwgbGlr ZSB1bmZvcnR1bmF0ZWx5IHRoZSBsYXJnZSBpbnRlcnJ1cHQgbWFwIGlzCj4gaW4gdGhhdCB0ZXJy aXRvcnkuCgpJIGZlZWwgdGhlIHNhbWUuCkV2ZW4gbGlzdGluZyBib3RoIGludGVycnVwdCBudW1i ZXJzIGluIFNPQ19QRVJJUEhFUkFMX0lSUShuYSwgbnIpCmlzIGEgcmlzayBmb3IgbWFraW5nIG1p c3Rha2VzLgoKU28gcGVyc29uYWxseSwgSSdtIGluIGZhdm9yIG9mIHRlYWNoaW5nIGR0YyBhcml0 aG1ldGljLCBzbyB3ZSBjYW4KaGFuZGxlIHRoZSBvZmZzZXQgaW4gU09DX1BFUklQSEVSQUxfSVJR KCkuCgpHcntvZXRqZSxlZXRpbmd9cywKCiAgICAgICAgICAgICAgICAgICAgICAgIEdlZXJ0Cgot LQpHZWVydCBVeXR0ZXJob2V2ZW4gLS0gVGhlcmUncyBsb3RzIG9mIExpbnV4IGJleW9uZCBpYTMy IC0tIGdlZXJ0QGxpbnV4LW02OGsub3JnCgpJbiBwZXJzb25hbCBjb252ZXJzYXRpb25zIHdpdGgg dGVjaG5pY2FsIHBlb3BsZSwgSSBjYWxsIG15c2VsZiBhIGhhY2tlci4gQnV0CndoZW4gSSdtIHRh bGtpbmcgdG8gam91cm5hbGlzdHMgSSBqdXN0IHNheSAicHJvZ3JhbW1lciIgb3Igc29tZXRoaW5n IGxpa2UgdGhhdC4KICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAtLSBMaW51cyBUb3J2 YWxkcwoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlu dXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qv1-f46.google.com (mail-qv1-f46.google.com [209.85.219.46]) (using TLSv1.2 with cipher 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[209.85.128.171]) by smtp.gmail.com with ESMTPSA id x26-20020a05620a0b5a00b006b5e1aeb777sm10555950qkg.43.2022.08.22.05.31.53 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Aug 2022 05:31:54 -0700 (PDT) Received: by mail-yw1-f171.google.com with SMTP id 00721157ae682-334dc616f86so288294517b3.8 for ; Mon, 22 Aug 2022 05:31:53 -0700 (PDT) X-Received: by 2002:a5b:6c1:0:b0:669:a7c3:4c33 with SMTP id r1-20020a5b06c1000000b00669a7c34c33mr18348478ybq.543.1661171513514; Mon, 22 Aug 2022 05:31:53 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20220815050815.22340-1-samuel@sholland.org> <20220815050815.22340-7-samuel@sholland.org> <20220815141159.10edeba5@donnerap.cambridge.arm.com> <3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com> <932aaefd-e2ca-ef26-bf30-e315fb271ec5@sholland.org> <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> In-Reply-To: <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> From: Geert Uytterhoeven Date: Mon, 22 Aug 2022 14:31:41 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree To: Conor Dooley Cc: Andre Przywara , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Albert Ou , Samuel Holland , Linux Kernel Mailing List , Jernej Skrabec , "Lad, Prabhakar" , Chen-Yu Tsai , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv , linux-sunxi@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Conor, On Mon, Aug 22, 2022 at 2:13 PM wrote: > On 22/08/2022 12:46, Geert Uytterhoeven wrote: > > On Sun, Aug 21, 2022 at 12:07 PM wrote: > >> On 21/08/2022 07:45, Icenowy Zheng wrote: > >>> =E5=9C=A8 2022-08-20=E6=98=9F=E6=9C=9F=E5=85=AD=E7=9A=84 17:29 +0000= =EF=BC=8CConor.Dooley@microchip.com=E5=86=99=E9=81=93=EF=BC=9A > >>>> On 20/08/2022 18:24, Samuel Holland wrote: > > >>>>> This is not feasible, due to the different #interrupt-cells. See > >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMc= FisGxHMBPUEa8nTMFpzw@mail.gmail.com/ > >>>>> > >>>>> Even if we share some file across architectures, you still have to > >>>>> update files > >>>>> in both places to get the interrupts properties correct. > >>>>> > >>>>> I get the desire to deduplicate things, but we already deal with > >>>>> updating the > >>>>> same/similar nodes across several SoCs, so that is nothing new. I > >>>>> think it would > >>>>> be more confusing/complicated to have all of the interrupts > >>>>> properties > >>>>> overridden in a separate file. > >>>> > >>>> Yeah, should maybe have circled back after that conversation, would > >>>> have been > >>>> nice but if the DTC can't do it nicely then w/e. > >>> > >>> Well, maybe we can overuse the facility of C preprocessor? > >>> > >>> e.g. > >>> > >>> ``` > >>> // For ARM > >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n > >>> // For RISC-V > >>> #define SOC_PERIPHERAL_IRQ(n) n > >>> ``` > >>> > >> > >> Geert pointed out that this is not possible (at least on the Renesas > >> stuff) because the GIC interrupt numbers are not the same as the > >> PLIC's & the DTC is not able to handle the addition: > >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFis= GxHMBPUEa8nTMFpzw@mail.gmail.com/ > > > > Without the ability to do additions in DTC, we could e.g. list both > > interrupts in the macro, like: > > > > // For ARM > > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na > > // For RISC-V > > #define SOC_PERIPHERAL_IRQ(na, nr) nr > > Do you think this is worth doing? Or are you just providing an > example of what could be done? Just some brainstorming... > Where would you envisage putting these macros? I forget the order > of the CPP operations that are done, can they be put in the dts? The SOC_PERIPHERAL_IRQ() macro should be defined in the ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file. > > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara wrote: > >> There are interrupt-maps for that: > >> sun8i-r528.dtsi: > >> soc { > >> #interrupt-cells =3D <1>; > >> interrupt-map =3D <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEV= EL_HIGH>, > >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL= _HIGH>, > >> .... > >> > >> sun20i-d1.dtsi: > >> soc { > >> #interrupt-cells =3D <1>; > >> interrupt-map =3D <0 18 &plic 18 IRQ_TYPE_LEVEL_HIG= H>, > >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>= , > >> > >> then, in the shared .dtsi: > >> uart0: serial@2500000 { > >> compatible =3D "snps,dw-apb-uart"; > >> ... > >> interrupts =3D <18>; > > > > Nice! But it's gonna be a very large interrupt-map. > > I quite like the idea of not duplicating files across the archs > if it can be helped, but not at the expense of making them hard to > understand & I feel like unfortunately the large interrupt map is > in that territory. I feel the same. Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr) is a risk for making mistakes. So personally, I'm in favor of teaching dtc arithmetic, so we can handle the offset in SOC_PERIPHERAL_IRQ(). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds