From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23AEEC433EF for ; Tue, 19 Apr 2022 08:56:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350228AbiDSI7O (ORCPT ); Tue, 19 Apr 2022 04:59:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237640AbiDSI7N (ORCPT ); Tue, 19 Apr 2022 04:59:13 -0400 Received: from mail-qk1-f170.google.com (mail-qk1-f170.google.com [209.85.222.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 966DF26131; Tue, 19 Apr 2022 01:56:31 -0700 (PDT) Received: by mail-qk1-f170.google.com with SMTP id s4so12996656qkh.0; Tue, 19 Apr 2022 01:56:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LjOeqfSZ1Rvs+3TDyOnSQqOYBJijn66+09FuaSFiHvE=; b=PCL8kYB+76UNj4OGyFlw7GzUg2FlKnTRxv4NMja8MWL9FE4lXQLkO2TEM5DMsrhB5c XAcKb00WLMXUjin5dzN7776jfPLwEC5NY6n2o8+84YljjxMn1Ers7XOz/6OQ6geLrEzI 3AEMHurD1EPaQzl2SgE38/Qc4nhsxCVsF6wdNPu+yIgH87vhvduoNAWGSTUa6hbnqYVp x9TVA8QClw9Q+j5a0XEM9w2xfaOiwWEY7F5TBojojwv8R//WhoEwZjujiBOz5hwGIMHo VFGC3TQQjZJukx+KAp5jzTdW2V+I8w+o5Ay+VzoBlR9p2dE2zwtZFb7OYFB0W8GV+6ON AkhQ== X-Gm-Message-State: AOAM531DSTTNYfim2nouNMuuyYy0472qkiTQKCp6mLTGWLuc/+/o08ac FwZiChBQTPW0bkQfzaR7MysTl5yQg+XoeA== X-Google-Smtp-Source: ABdhPJxsIcdkjefaIaP0LmluCuCeLfScqY8uGaGmdlqDNte9QTCQfS/4R4G1Txjpty1oeJkpt+3ZTg== X-Received: by 2002:a05:620a:1431:b0:69e:59be:1ece with SMTP id k17-20020a05620a143100b0069e59be1ecemr8808830qkj.600.1650358590603; Tue, 19 Apr 2022 01:56:30 -0700 (PDT) Received: from mail-yw1-f178.google.com (mail-yw1-f178.google.com. [209.85.128.178]) by smtp.gmail.com with ESMTPSA id e15-20020ac8670f000000b002e22d9c756dsm8338587qtp.30.2022.04.19.01.56.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Apr 2022 01:56:30 -0700 (PDT) Received: by mail-yw1-f178.google.com with SMTP id 00721157ae682-2ef4a241cc5so157765727b3.2; Tue, 19 Apr 2022 01:56:30 -0700 (PDT) X-Received: by 2002:a0d:e743:0:b0:2eb:3106:9b32 with SMTP id q64-20020a0de743000000b002eb31069b32mr14815567ywe.512.1650358590048; Tue, 19 Apr 2022 01:56:30 -0700 (PDT) MIME-Version: 1.0 References: <20220328064931.11612-1-biju.das.jz@bp.renesas.com> <20220328064931.11612-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20220328064931.11612-2-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 19 Apr 2022 10:56:18 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings To: Biju Das Cc: David Airlie , Daniel Vetter , Rob Herring , DRI Development , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , Linux-Renesas Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Biju, On Mon, Mar 28, 2022 at 8:49 AM Biju Das wrote: > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It > can operate in DSI mode, with up to four data lanes. > > Signed-off-by: Biju Das Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -0,0 +1,175 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L MIPI DSI Encoder > + > +maintainers: > + - Biju Das > + > +description: | > + This binding describes the MIPI DSI encoder embedded in the Renesas > + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with > + up to four data lanes. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L Do you want to define SoC-specific compatible values, or can the IP revision be read from the hardware? The rest LGTM (I'm no MIPI-DSI expert), so Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6817C433F5 for ; Tue, 19 Apr 2022 08:56:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3646D10E8F0; Tue, 19 Apr 2022 08:56:33 +0000 (UTC) Received: from mail-qt1-f175.google.com (mail-qt1-f175.google.com [209.85.160.175]) by gabe.freedesktop.org (Postfix) with ESMTPS id 598BE10E8F0 for ; Tue, 19 Apr 2022 08:56:32 +0000 (UTC) Received: by mail-qt1-f175.google.com with SMTP id x24so3282102qtq.11 for ; Tue, 19 Apr 2022 01:56:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LjOeqfSZ1Rvs+3TDyOnSQqOYBJijn66+09FuaSFiHvE=; b=VuTaN5N0a//ISboX4QP6Dzfbb2cQtLFILNkjYYZYs9OJD1OqmGyBHzpAGZzbGy8POe 1yTwoMv7rIpUuooW2MbRwPHJdE26+x0H6NZkbn1DcUFSRZ8U+fG3nfFKisZdbMlX7xvc p5eRiFLNtkSLLisKPQEOoRDrbockAgnchORg3/dwdXAcN+gj7iA+flFjeTrCJHHdpzL/ 9k0xH3UxVU+tadOwEPicE3qoj5rrjyZFnEmXcSdWDUUDn+oFnHsDlfOaZH1n3xYZY2fw lMiuqWARlhArSvSIq6X0UiI64aHjvXK5DpwNNKe/+DTc8fByYb9p3pnrAN3AiI04coB0 ka3A== X-Gm-Message-State: AOAM531vUqBpQr9b+26BEWU9tP5VNz2eb43q4iLqGlHdJTTsriYwAvRO THPkXCvmERMqowtPCdWrjsPHCTURToyAMg== X-Google-Smtp-Source: ABdhPJypQ7bbuI0sUtsTetwuP4Eygq2D890idzsb/n+IIVRfYXGnnu/nN4Ug2ICdIYCs6CbMBZcPlA== X-Received: by 2002:ac8:5d8c:0:b0:2e1:e196:326a with SMTP id d12-20020ac85d8c000000b002e1e196326amr9517738qtx.475.1650358591027; Tue, 19 Apr 2022 01:56:31 -0700 (PDT) Received: from mail-yw1-f181.google.com (mail-yw1-f181.google.com. [209.85.128.181]) by smtp.gmail.com with ESMTPSA id d22-20020a05622a101600b002f1f139d83bsm6096870qte.84.2022.04.19.01.56.30 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Apr 2022 01:56:30 -0700 (PDT) Received: by mail-yw1-f181.google.com with SMTP id 00721157ae682-2ebf4b91212so164713367b3.8 for ; Tue, 19 Apr 2022 01:56:30 -0700 (PDT) X-Received: by 2002:a0d:e743:0:b0:2eb:3106:9b32 with SMTP id q64-20020a0de743000000b002eb31069b32mr14815567ywe.512.1650358590048; Tue, 19 Apr 2022 01:56:30 -0700 (PDT) MIME-Version: 1.0 References: <20220328064931.11612-1-biju.das.jz@bp.renesas.com> <20220328064931.11612-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20220328064931.11612-2-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 19 Apr 2022 10:56:18 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings To: Biju Das Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Chris Paterson , Geert Uytterhoeven , David Airlie , Prabhakar Mahadev Lad , DRI Development , Biju Das , Linux-Renesas , Rob Herring Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Biju, On Mon, Mar 28, 2022 at 8:49 AM Biju Das wrote: > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It > can operate in DSI mode, with up to four data lanes. > > Signed-off-by: Biju Das Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -0,0 +1,175 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L MIPI DSI Encoder > + > +maintainers: > + - Biju Das > + > +description: | > + This binding describes the MIPI DSI encoder embedded in the Renesas > + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with > + up to four data lanes. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L Do you want to define SoC-specific compatible values, or can the IP revision be read from the hardware? The rest LGTM (I'm no MIPI-DSI expert), so Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds