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[209.85.128.172]) by smtp.gmail.com with ESMTPSA id h124-20020a376c82000000b0069fc13ce203sm2553104qkc.52.2022.05.12.00.39.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 May 2022 00:39:25 -0700 (PDT) Received: by mail-yw1-f172.google.com with SMTP id 00721157ae682-2f7b815ac06so46657427b3.3; Thu, 12 May 2022 00:39:25 -0700 (PDT) X-Received: by 2002:a81:6588:0:b0:2f8:b75e:1e1a with SMTP id z130-20020a816588000000b002f8b75e1e1amr30053583ywb.358.1652341165120; Thu, 12 May 2022 00:39:25 -0700 (PDT) MIME-Version: 1.0 References: <20220511183210.5248-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220511183210.5248-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220511183210.5248-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 12 May 2022 09:39:13 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt To: Lad Prabhakar Cc: Linus Walleij , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Bartosz Golaszewski , Philipp Zabel , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Phil Edworthy , Biju Das , Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Prabhakar, On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar wrote: > Add IRQ domian to RZ/G2L pinctrl driver to handle GPIO interrupt. domain > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be > used as IRQ lines at given time. Selection of pins as IRQ lines at a given time > is handled by IA55 (which is the IRQC block) which sits in between the > GPIO and GIC. > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) > { > struct device_node *np = pctrl->dev->of_node; > struct gpio_chip *chip = &pctrl->gpio_chip; > const char *name = dev_name(pctrl->dev); > + struct irq_domain *parent_domain; > struct of_phandle_args of_args; > + struct device_node *parent_np; > + struct gpio_irq_chip *girq; > int ret; > > + parent_np = of_irq_find_parent(np); > + if (!parent_np) > + return -ENXIO; > + > + parent_domain = irq_find_host(parent_np); > + of_node_put(parent_np); > + if (!parent_domain) > + return -EPROBE_DEFER; > + > ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); > if (ret) { > dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); > @@ -1138,6 +1330,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) > chip->base = -1; > chip->ngpio = of_args.args[2]; > > + girq = &chip->irq; > + girq->chip = &rzg2l_gpio_irqchip; > + girq->fwnode = of_node_to_fwnode(np); > + girq->parent_domain = parent_domain; > + girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; > + girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; > + girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; > + girq->ngirq = RZG2L_TINT_MAX_INTERRUPT; > + I think you need to provide a .init_valid_mask() callback, as gpiochip_irqchip_remove() relies on that for destroying interrupts. However, the mask will need to be dynamic, as GPIO interrupts can be mapped and unmapped to one of the 32 available interrupts dynamically, right? I'm not sure if that can be done easily: if gpiochip_irqchip_irq_valid() is ever called too early, before the mapping is done, it would fail. > pctrl->gpio_range.id = 0; > pctrl->gpio_range.pin_base = 0; > pctrl->gpio_range.base = 0; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds