From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74088C48BE8 for ; Tue, 15 Jun 2021 10:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57E5B61450 for ; Tue, 15 Jun 2021 10:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231486AbhFOK1I (ORCPT ); Tue, 15 Jun 2021 06:27:08 -0400 Received: from mail-ua1-f52.google.com ([209.85.222.52]:46630 "EHLO mail-ua1-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231384AbhFOK1I (ORCPT ); Tue, 15 Jun 2021 06:27:08 -0400 Received: by mail-ua1-f52.google.com with SMTP id p1so6480384uam.13; Tue, 15 Jun 2021 03:25:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xslGpHfV+IcRpIJzyLdYtz16ALOn8/WMq83lttKXk9M=; b=uNIEzrrnOkv4NRA1OpNlrHcRSJU6nWcNY/hE9Hd8gAhfGAD8WyMxuvpWy5Bfb6lfgG V2yT9MGOdey/xmMMN/URml1hv+oGyYljPOQ+kJuQlf4fwYz4vM0Ut5StoC0rfR8l17BS msj/UeBH6XWFeUqo7jq1PVW9CI0+7XE3PtxBMId6KHPoWtVjQiDaTVi+XnxqXgGP1Bfx 0KsnVBGXoHCAtKtQybd8AET24JStAk5fUgKyTg+ljssP3M9tr60hFoEVuD/EtAZTikII s2VB0pf4ZSVzCTFkQ/fYNap3i5ndtimlpGfmBZexAQiky2RywY0BxbrYBPa3uAkyWcLw i9IA== X-Gm-Message-State: AOAM532wVgQhUtnBe2ec6eqq5E2H1qJVq4XVj7AgRWsalQ9l22/EQcrN Uj0RMRmj5H9cUQcsOSARuufR+fWWXO++xJwTsvA= X-Google-Smtp-Source: ABdhPJyjgVMHJnMLTjlpbIOMYr4+M09yxQ0L9lR/lFuPp93QPmgg6JeGX67T5wRbLTCXJkamVTyUZ8yI9DPKwvUTPTw= X-Received: by 2002:ab0:b09:: with SMTP id b9mr16490374uak.58.1623752703257; Tue, 15 Jun 2021 03:25:03 -0700 (PDT) MIME-Version: 1.0 References: <20210611134642.24029-1-biju.das.jz@bp.renesas.com> <20210611134642.24029-3-biju.das.jz@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 15 Jun 2021 12:24:52 +0200 Message-ID: Subject: Re: [PATCH 2/6] drivers: clk: renesas: r9a07g044-cpg: Add USB clocks To: Laurent Pinchart Cc: Biju Das , Michael Turquette , Stephen Boyd , Linux-Renesas , linux-clk , Chris Paterson , Biju Das , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Laurent, On Tue, Jun 15, 2021 at 11:57 AM Laurent Pinchart wrote: > On Tue, Jun 15, 2021 at 11:53:37AM +0200, Geert Uytterhoeven wrote: > > On Tue, Jun 15, 2021 at 11:49 AM Laurent Pinchart > > wrote: > > > On Tue, Jun 15, 2021 at 10:58:57AM +0200, Geert Uytterhoeven wrote: > > > > On Mon, Jun 14, 2021 at 2:26 PM Geert Uytterhoeven wrote: > > > > > On Fri, Jun 11, 2021 at 3:46 PM Biju Das wrote: > > > > > > Add clock entries for USB{0,1}. > > > > > > > > > > > > Signed-off-by: Biju Das > > > > > > Reviewed-by: Lad Prabhakar > > > > > > > > > > Thanks for your patch! > > > > > > > > > > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > > > > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > > > > > @@ -88,6 +88,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { > > > > > > DEF_MOD("dmac", R9A07G044_CLK_DMAC, > > > > > > R9A07G044_CLK_P1, > > > > > > 0x52c, (BIT(0) | BIT(1)), (BIT(0) | BIT(1))), > > > > > > + DEF_MOD("usb0", R9A07G044_CLK_USB0, > > > > > > + R9A07G044_CLK_P1, > > > > > > + 0x578, (BIT(0) | BIT(2) | BIT(3)), (BIT(0) | BIT(2) | BIT(3))), > > > > > > + DEF_MOD("usb1", R9A07G044_CLK_USB1, > > > > > > + R9A07G044_CLK_P1, > > > > > > + 0x578, (BIT(1) | BIT(3)), (BIT(1) | BIT(3))), > > > > > > DEF_MOD("scif0", R9A07G044_CLK_SCIF0, > > > > > > R9A07G044_CLK_P0, > > > > > > 0x584, BIT(0), BIT(0)), > > > > > > > > > > While the above matches the datasheet, I see a problem with the > > > > > implementation. As BIT(3) of the CPG_{CLKON,CLKMON,RST}_USB is shared by > > > > > the two USB2.0 channels, disabling USB_PCLK or asserting USB_PRESETN > > > > > will affect both channels. So it looks like you need special handling > > > > > to make sure that doesn't happen while the other channel is in use. > > > > > > > > > > Or am I missing something? > > > > > > > > I'm getting the impression we do have to model the individual bits > > > > as separate clocks (and resets). That would solve the problem with > > > > the shared USB_PCLK, as the clock framework will take care of keeping > > > > it enabled when at least one channel is in use. > > > > > > > > Besides USB, SDHI has 4 clock bits, which we definitely don't want > > > > to control together, as the card detect clock must not be stopped > > > > while suspended. > > > > However, the exception to the rule is Ethernet: each channel has > > > > 2 clocks, but only a single bit to control, so this needs a custom > > > > single-gate-for-dual-clock driver. > > > > > > Does it ? Can't the same clock be referenced twice in DT ? > > > > Yes, you can reference the same clock twice. But what's the point? > > If they're two different clocks, DT should reference two different > > clocks. But the single bit should correspond to the ORed value of > > the two clock enable states. > > > > Or do you mean something different? > > If the device has two clock inputs, I'd model the two clocks separately > in the DT bindings. If those two clocks are gated by the same bit in an > SoC, we have two options to model the integration: > > - Create a driver that registers different clocks with the same gating > bit. We'll have two clocks to reference in DT. OK, that's what I suggested. > - Model both clocks as a single clock in the clock driver, and reference > that clock twice in DT. This is simpler, but only works if the > consumer doesn't need to query the clock rate. Modelling them as a single clock is how the current RZ/G2L clock driver would implement it. But why bother referencing it twice in DT? renesas,ether*.yaml (assuming the Ethernet block is compatible) documents a single clock only (ignoring optional refclk), and the driver doesn't care about the clock rate. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds