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[209.85.217.46]) by smtp.gmail.com with ESMTPSA id u6sm8521559vku.15.2022.02.23.03.27.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Feb 2022 03:27:22 -0800 (PST) Received: by mail-vs1-f46.google.com with SMTP id d11so2767979vsm.5; Wed, 23 Feb 2022 03:27:21 -0800 (PST) X-Received: by 2002:a05:6102:4411:b0:31b:6df1:3b80 with SMTP id df17-20020a056102441100b0031b6df13b80mr11543425vsb.5.1645615641619; Wed, 23 Feb 2022 03:27:21 -0800 (PST) MIME-Version: 1.0 References: <20220222103437.194779-1-miquel.raynal@bootlin.com> <20220222103437.194779-2-miquel.raynal@bootlin.com> In-Reply-To: <20220222103437.194779-2-miquel.raynal@bootlin.com> From: Geert Uytterhoeven Date: Wed, 23 Feb 2022 12:27:10 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/8] dt-bindings: dma: Introduce RZN1 dmamux bindings To: Miquel Raynal Cc: Vinod Koul , Andy Shevchenko , dmaengine , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Magnus Damm , Gareth Williams , Phil Edworthy , Stephen Boyd , Michael Turquette , linux-clk , Thomas Petazzoni , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Hi Miquel, On Tue, Feb 22, 2022 at 11:34 AM Miquel Raynal wrote: > The Renesas RZN1 DMA IP is a based on a DW core, with eg. an additional > dmamux register located in the system control area which can take up to > 32 requests (16 per DMA controller). Each DMA channel can be wired to > two different peripherals. > > Signed-off-by: Miquel Raynal Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/N1 DMA mux > + > +maintainers: > + - Miquel Raynal > + > +allOf: > + - $ref: "dma-router.yaml#" > + > +properties: > + compatible: > + const: renesas,rzn1-dmamux Do we want an SoC-specific compatible value, too? See also my comments on the dmamux driver. > + > + '#dma-cells': > + const: 6 > + description: > + The first four cells are dedicated to the master DMA controller. The fifth > + cell gives the DMA mux bit index that must be set starting from 0. The > + sixth cell gives the binary value that must be written there, ie. 0 or 1. > + > + dma-masters: > + minItems: 1 > + maxItems: 2 > + > + dma-requests: > + const: 32 Do we need this in DT? It depends on the actual dmamux hardware, and is (currently) the register width of the CFG_DMAMUX register. The rest LGTM (I'm no dma-router expert),so with the above clarified: Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds