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[209.85.219.176]) by smtp.gmail.com with ESMTPSA id q21-20020ac84515000000b003a7f3c4dcdfsm5641135qtn.47.2022.12.19.00.40.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Dec 2022 00:40:21 -0800 (PST) Received: by mail-yb1-f176.google.com with SMTP id 192so8667262ybt.6; Mon, 19 Dec 2022 00:40:21 -0800 (PST) X-Received: by 2002:a25:7104:0:b0:702:90b4:2e24 with SMTP id m4-20020a257104000000b0070290b42e24mr14806510ybc.365.1671439221181; Mon, 19 Dec 2022 00:40:21 -0800 (PST) MIME-Version: 1.0 References: <20221216205028.340795-1-biju.das.jz@bp.renesas.com> <20221216205028.340795-5-biju.das.jz@bp.renesas.com> In-Reply-To: <20221216205028.340795-5-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Mon, 19 Dec 2022 09:40:09 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v10 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver To: biju.das.jz@bp.renesas.com Cc: William Breathitt Gray , linux-iio@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi Biju, On Fri, Dec 16, 2022 at 9:50 PM Biju Das wrote: > Add RZ/G2L MTU3a counter driver. This IP supports the following > phase counting modes on MTU1 and MTU2 channels > > 1) 16-bit phase counting modes on MTU1 and MTU2 channels. > 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. > > This patch adds 3 counter value channels. > count0: 16-bit phase counter value channel on MTU1 > count1: 16-bit phase counter value channel on MTU2 > count2: 32-bit phase counter value channel by cascading > MTU1 and MTU2 channels. > > The external input phase clock pin for the counter value channels > are as follows: > count0: "MTCLKA-MTCLKB" > count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > > Use the sysfs variable "external_input_phase_clock_select" to select the > external input phase clock pin and "cascade_counts_enable" to enable/ > disable cascading of channels. > > Signed-off-by: Biju Das > --- > v9->v10: Thanks for the update! > --- /dev/null > +++ b/drivers/counter/rz-mtu3-cnt.c > +static int rz_mtu3_count_read(struct counter_device *counter, > + struct counter_count *count, u64 *val) > +{ > + struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); > + struct rz_mtu3_cnt *const priv = counter_priv(counter); > + > + mutex_lock(&priv->lock); > + if (ch->is_busy && !priv->count_is_enabled[count->id]) { > + mutex_unlock(&priv->lock); > + return -EINVAL; > + } > + > + if (rz_mtu3_is_counter_invalid(counter, count->id)) { > + mutex_unlock(&priv->lock); > + return -EBUSY; > + } As the locking and the above two checks are duplicated multiple times, perhaps they can be replaced by an rz_mtu3_lock_if_counter_is_valid() helper function? > +static int rz_mtu3_count_function_read(struct counter_device *counter, > + struct counter_count *count, > + enum counter_function *function) > +{ > + struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); > + struct rz_mtu3_cnt *const priv = counter_priv(counter); > + int ret; > + > + mutex_lock(&priv->lock); > + if (ch->is_busy && !priv->count_is_enabled[count->id]) { > + mutex_unlock(&priv->lock); > + return -EINVAL; > + } rz_mtu3_lock_if_count_is_disabled() helper? (can also be called by rz_mtu3_lock_if_counter_is_valid()) > +static int rz_mtu3_cascade_counts_enable_set(struct counter_device *counter, > + u8 cascade_enable) > +{ > + struct rz_mtu3_cnt *const priv = counter_priv(counter); > + > + mutex_lock(&priv->lock); > + if (priv->ch->is_busy && !rz_mtu3_is_ch0_enabled(priv)) { > + mutex_unlock(&priv->lock); > + return -EINVAL; > + } rz_mtu3_lock_if_count_is_disabled() helper? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds